Envisia HDL Modeling Reference
Verilog Modeling Styles
`define BITS 8
`define LIB TECH
module `XYZ_`BITS_`LIB ();
To handle such usage, the following extension to the syntax is used by VPP to evaluate the module name to AND_8_TECH.
module `{XYZ}_`{BITS}_`{LIB} ();
Command Line Options
VPP supports the following command line options:
■I …/incl
Shows the directories of where to search for the include files.
■I …/incl
Provides UNIX cpp compatibility (no space between option, path).
■D abc=12
Defines abc to be 12; similar to +define in verilog-xl.
■Dabc=12
Provides UNIX cpp compatibility (no space between option, value).
■nolinenum
States that `line will not be generated in the output.
VPP Flag Attribute
The VPP flag attribute is shown below:
set_global vpp_arg = “-I …/include -DSYNTH”
Verilog-Related Commands and Globals
Table 2-2 provides the Verilog-related ac_shell commands. Table 2-3 provides the Verilogspecific ac_shell global variables used with the set_global command; the default values
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Envisia HDL Modeling Reference
Verilog Modeling Styles
are shown in parentheses. Please see the Envisia and Ambit Command Reference for a complete list of commands and globals and their descriptions and examples.
Table 2-2 Verilog ac_shell Commands
Command |
Description |
|
|
read_verilog |
Analyze Verilog source files. |
write_verilog |
Write Verilog netlist. |
get_hdl_type |
For a given module, returns the file type, either Verilog or |
|
VHDL. |
get_hdl_hierarchy |
Returns a hierarchical list of modules in the design and a list |
|
of their paramterized and non-parameterized instances. |
get_hdl_file |
Returns the file name corresponding to the module. |
get_hdl_top_level |
Returns a list of top level module names. |
|
|
Table 2-3 Verilog-Specific Global Variables
Command |
Description (Defaults) |
|
|
hdl_verilog_out_columns |
Specify the maximum line length for writing out Verilog |
|
netlist in files. (80) |
hdl_verilog_out_compact |
Write out compact files for Verilog netlist output. If set to |
|
false, only one statement is written per line. (true) |
hdl_verilog_out_ |
Implicit wires in Verilog do not require a declaration. If |
declare_implicit_wires |
set to true the declarations for implicit wires are also |
|
written. (false) |
hdl_verilog_out_prim |
When set to true, primitive Verilog operators are written |
|
instead of the ATL equivalent components. ( true) |
hdl_verilog_out_source_ Keep track of the RTL source code. (false) |
|
track |
|
hdl_verilog_out_ |
Select the netlisting style for unconnected instance pins. |
unconnected_style |
(none) |
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Verilog Modeling Styles
Table 2-3 Verilog-Specific Global Variables, continued
Command |
Description (Defaults) |
|
|
hdl_verilog_out_use_ |
Specify constant signals (1 or 0) as supply signals |
supply |
(supply1 or supply0). If set to true, the generated Verilog |
|
code will contain supply declarations. If set to false, the |
|
literal constants 1’b1 and 1’b0 are used for |
|
connection to power and ground. (false) |
hdl_verilog_vpp_arg |
Pass arguments to VPP. The typical argument passed is |
|
the search path; options within the argument string must |
|
be separated by one or more spaces. |
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