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VHDL Modeling Style

signal curr_state: std_logic_vector(2 downto 0); signal next_state: std_logic_vector(2 downto 0); process(curr_state)

subtype INT02 is integer range 0 to 2; begin

for I in INT02 loop

next_state(2-I) <= curr_state(I); end loop;

end process;

Synthesis Directives

BuildGates synthesis provides a variety of synthesis directives to control the synthesis process. Synthesis directives perform code selection or specify how the set and reset pins of a register are wired. Two forms of VHDL synthesis directivesare supported:

■Attributes

Define VHDL attributes attached to appropriate objects in the source VHDL.

■Meta-comments

Define the VHDL comments embedded in the VHDL source code. These directives begin with the following keywords: ambit synthesis

Note: When a comment is used for specifying a synthesis directive, that comment should not contain any extra characters other than what is necessary for the synthesis directive.

This section describes the following synthesis directives:

■Code Selection Directives on page 60

■Architecture Selection Directive on page 61

■case Statement Directive on page 61

■Enumeration Encoding Directive on page 62

■Entity Template Directive on page 62

■Function and Procedure Mapping Directives on page 63

■Signed Type Directive on page 63

■Resolution Function Directives on page 64

■Type Conversion Directives on page 64

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VHDL Modeling Style

Set and Reset Synthesis Directives on page 65

Process Directives on page 67

Signal Directives on page 69

Signals in a Process Directive on page 71

Code Selection Directives

By default, BuildGates synthesis compiles all VHDL code from a file. The code selection synthesis directives are used in pairs around VHDL code that should not be compiled for synthesis.

Synthesis On and Synthesis Off Directives

All the code following the synthesis directive -- ambit synthesis off up to and including the synthesis directive -- ambit synthesis on is ignored by the tool. However the code between the two directives will be checked for syntactic correctness.

For example, you may add assertions in your model for debug purposes that is not synthesized. If the assertions are surrounded by the synthesis on and synthesis off directives, the tool ignores them for synthesis but verifies the syntax between the directives

(see below).

function DIVIDE (L, R: integer) return integer is variable RESULT: integer;

begin

--ambit synthesis off assert (R /= 0)

report "Attempt to Divide by Zero Unsupported !!!"

severity ERROR;

--ambit synthesis on

RESULT:= L/R; return (RESULT);

end DIVIDE;

Translate On and Translate Off Directives

The translate on and translate off code selection directives are used around

VHDL code that should be completely ignored by the VHDL parser and not synthesized by

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VHDL Modeling Style

the tool. All the code following the synthesis directive ambit translate off up to and including the synthesis directive ambit translate on is ignored by the tool even if it contains syntax errors.

Architecture Selection Directive

This directive is used to select different types of architectures for arithmetic and comparator

(relational) operators. At present, there are three architectures available:

■Carry Lookahead

■Conditional Sum

■Ripple Carry

For VHDL, you specify the architecture selection directive immediately after the selected operator is used. For example:

-- use Ripple Carry adder

x <= a + b; -- ambit synthesis architecture = ripple

If there are multiple operators in the expression, the directive must be placed immediately following the desired operator. For example:

--implement subtractor with ripple-carry architecture x1 <= a + b - c; -- ambit synthesis architecture = ripple

--implement adder with ripple-carry and substractor

--with carry lookahead architecture

x2 <= a + -- ambit synthesis architecture = ripple b - c; -- ambit synthesis architecture = cla

case Statement Directive

If you use a case statement as a multiplexor instead of random logic, then the mux directive should be specified for the case statement. Refer to the following model:

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VHDL Modeling Style

-- "110" not specified.

when "111" => z <= d(7);

when others => null;

end case;

end process;

Enumeration Encoding Directive

This directive allows the user to override the default encoding of enumeration literals as shown below.

type COLOR is (RED, BLUE, GREEN, YELLOW);

attribute ENUM_ENCODING: string;

attribute ENUM_ENCODING of COLOR: type is "10 00 11 01”;

In the model above, the literals RED and YELLOW would normally be encoded as 00 and 11, respectively, (corresponding to their position in the type COLOR, starting from 0). Because of the ENUM_ENCODING attribute, RED and YELLOW are encoded as 10 and 01, respectively. The attribute ENUM_ENCODING is declared in the package: ambit.attributes.

The ENUM_ENCODING value string must contain as many encodings as there are literals in the corresponding enumeration type. All encodings must contain only 0’s or 1’s and should have an identical number of bits.

Entity Template Directive

When an entity is written with generic declarations for use as a template, only the instantiated, parameterized design needs to be synthesized. The TEMPLATE directive on an entity indicates that the template entity is not to be synthesized except in the context of an instantiation. When the TEMPLATE directive is used, it must be specified as TRUE in the entity declaration as shown below.

use ambit.attributes.all; entity FOO is

generic (Width : integer := 64);

port (DIN : bit_vector (Width - 1 downto 0); DOUT : bit_vector (Width - 1 downto 0));

attribute TEMPLATE of FOO: entity is TRUE; end FOO;

By designating entities as templates, do_build_generic will run faster since it can eliminate synthesizing the template entities that are not actually used in the hierarchical