Envisia HDL Modeling Reference

Finite State Machine Structure and Optimization

Extracting the State Transition Table for the FSM

After you have read the design data into the BuildGates synthesis software, you can extract the state transition table for the FSM.

In ac_shell (or pks_shell if applicable), enter the following command:

do_build_generic -extract_fsm

Note: BuildGates synthesis software only invokes the FSM optimization flow when the do_build_generic command is used with the -extract_fsm option.

Viewing the State Transition Table for the FSM

After you extract the state transition table for the FSM, you can view it. The state transition table contains information about equivalent states, initial states, and state encodings.

In ac_shell (or pks_shell if applicable), enter the following command:

report_fsm -state

The following sections provide information you need to know when using the FSM flow in the BuildGates synthesis tool.

■FSM Optimization Features on page 92

■Verilog and VHDL FSM Directives on page 95

■Verification of Synthesized FSMs on page 104

FSM Optimization Features

This section provides high-level information about the FSM optimization flow that enables you to achieve better results from your optimizations. Below is a list of the FSM optimizations listed by the order of their importance and the impact they have on the quality of results

(QOR). You can invoke these FSM optimizations using Cadence synthesis pragmas.

■Unreachable State Removal on page 93

■State Assignment or Re-Encoding on page 93

■State Minimization on page 95

■Terminal State Check on page 95

Envisia HDL Modeling Reference

Finite State Machine Structure and Optimization

Unreachable State Removal

This optimization tells the BuildGates synthesis tool to treat all unreachable states, including the set of invalid states represented by the default case, as don’t cares. If you do not specify the actions indicated by the default case statement representing the FSM, they are honored by the software. The full_case pragma is ignored for the case statement that defines the

FSM. If the invalid states are to be treated as don’t cares, you must use the following Cadence pragma:

Note: This option reduces the run time because BuildGates synthesis software takes special care to handle the actions from invalid states (represented by the default case). For a sparsely encoded machine, the number of unreachable (invalid) states could be large, leading to longer runtimes. This option is also recommended for shorter runtimes.

State Assignment or Re-Encoding

Although you can provide a default state assignment using the enum directive, this optimization provides many encoding styles that often yield better quality results for area and timing. You can invoke the various encoding styles using the following Cadence pragma:

// ambit synthesis state-vector state_reg -encoding encoding_style

Table 4-1 shows the state_vector encoding options available with BuildGates synthesis software.

Table 4-1 state_vector Encoding Options

random assignment of states

Envisia HDL Modeling Reference

Finite State Machine Structure and Optimization