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Verilog Modeling Styles

for (i = 0; i <= 7; i = i + 1)

out[7-i] = in[i];

where i is declared as integer, out is an 8-bit reg and in is an 8-bit wire or reg.

The for statement is expanded to repeat the operations over the range of the index.

Therefore, the for statement model above is treated in an equivalent manner to the following operations:

out[7] = in[0]; out[6] = in[1]; out[5] = in[2]; out[4] = in[3]; out[3] = in[4]; out[2] = in[5]; out[1] = in[6]; out[0] = in[7];

The following forms of the for statement are supported in Verilog:

for (index = low; index < high; index = index+step) for (index = low; index <= high; index = index+step) for (index = high; index > low; index = index-step) for (index = high; index >= low; index = index-step)

where index is declared as integer or reg; high, low and step are integers, and high must be greater than or equal to low. High, low and step must evaluate to constant numbers at compile time. An error message is generated if one of them does not evaluate to a constant number.

Note: A for statement can be nested inside another for statement, but cannot contain any form of timing control or event control. Therefore, the following usage of the for statement is illegal:

for (i = 0; i <= 7; i = i + 1)

@(posedge clk) out[7-i] = in[i] ;

Synthesis Directives

Synthesis directives are comments. These comments should not to be confused with Verilog HDL compiler directives that begin with ‘.

The following two forms of Verilog synthesis directives are supported with Ambit BuildGates synthesis:

■Short comments that terminate at the end of the line

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Verilog Modeling Styles

// ambit synthesis <comment>

■Long comments that extend beyond one line

/* ambit synthesis <comment> */

Each comment begins with the words ambit synthesis. Comments used to specify synthesis directives should not contain any extra characters other than those necessary for the synthesis directive.

Note: When a comment is used for specifying a synthesis directive, that comment should not contain any extra characters other than what is necessary for the synthesis directive.

This section describes the following synthesis directives:

■Code Selection Directives on page 32

■Architecture Selection Directive on page 33

■case Statement Directives on page 34

Full Case Directive on page 34

Parallel Case Directive on page 35

Mux Case Directive on page 36

■Module Template Directive on page 36

■Function and Task Mapping Directives on page 36

■Set and Reset Synthesis Directives on page 37

Block Directives on page 38

Signal Directives on page 40

Signals in a Block Directive on page 42

Code Selection Directives

By default, BuildGates synthesis compiles all HDL code from a file. The code selection synthesis directives are used in pairs around HDL code that should not be compiled for synthesis.

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Verilog Modeling Styles

Synthesis On and Off Directives

All the code following the synthesis directive // ambit synthesis off up to and including the synthesis directive // ambit synthesis on is ignored by the tool.

In the Verilog example below, you may add certain initialization code in your model for debug purposes that is not synthesized. If the initial block is surrounded by these synthesis directives, the tool will skip over the entire block.

//ambit synthesis off initial begin cond_flag = 0 ;

$display(“cond_flag cleared at the beginning.”) ; end

//ambit synthesis on

always @(posedge clock) if (cond_flag)

...

Architecture Selection Directive

This directive is used to select different types of architectures for arithmetic and comparator (relational) operators. There are three architectures available

■Carry Lookahead

■Conditional Sum

■Ripple Carry

For Verilog, you specify the architecture selection directive immediately after the selected operator is used. Refer to the following models:

assign x = a + /* ambit synthesis architecture = ripple */ b;

If there are multiple operators in the expression, the directive must be placed immediately following the desired operator. For example:

// implement subtractor with ripple-carry architecture

x1 <= a + b - /* ambit synthesis architecture = ripple */ c;

//implement adder with ripple-carry and subtractor

//with carry lookahead architecture

x2 <= a + /* ambit synthesis architecture = ripple */ b - /* ambit synthesis architecture = cla */ c;

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case Statement Directives

A case statement can be interpreted in many ways. The default interpretation is that there is a priority decoding of the case labels in the order listed in the model. In other words, the case statement is interpreted as a nested if-else statement.

The case statement synthesis directive provides the mechanism to modify the default interpretation to capture the design intent. The directive is used as follows:

// ambit synthesis case = value

where value = full, parallel, or mux

This synthesis directive can take one, two, or three comma-separated values as listed above. The order of the values is unimportant. This directive must appear immediately after the case expression.

If the case statement has sufficient information, the following synthesis directives are automatically inferred even if they are not included in the code:

■Full Case Directive on page 34

■Parallel Case Directive on page 35

■Mux Case Directive on page 36

Full Case Directive

If the synthesis directive value includes full, the case statement is interpreted to mean that the case expression can evaluate to only those values specified by the case labels in the case statement. This implies that all other possible values of the case expression can be treated as don’t care conditions. This further implies that there is no need for a default clause in the case statement and no latch should be inferred. The following is an example of using the full case synthesis directive:

case (arith_opcode) // ambit synthesis case = full 4’b0000 : result = 32’h0 ;// clear

4’b0001 : result = src1 + src2 ;// add 4’b0010 : result = src1 + 1’b1 ;// inc 4’b1001 : result = src1 - src2 ;// sub1 4’b1101 : result = src2 - src1 ;// sub2 4’b1010 : result = src1 - 1’b1 ;// dec

endcase

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Note: The latch inference is suppressed using the full case directive only if the procedural assignments in each individual case item is made to all the variables modified in the case statement.

For example, in the case statement below, the second case item does not modify reg2, causing it to be inferred as a latch (to retain last value).

case (cntr_sig) // ambit synthesis case = full 2’b00 : begin reg1 = 0 ; reg2 = v_field ; end

2’b01 : reg1 = v_field ; // latch inferred for reg2 2’b10 : begin reg1 = v_field ; reg2 = 0 ; end

endcase

If the full case synthesis directive is incorrectly used, RTL-and gate-level simulation results in a mismatch. When an unspecified case occurs during the simulation, the RTL model will preserve the value of the variable because it is a reg type variable. The gate-level simulation would have implemented combinational logic, possibly generating an incorrect output.

Parallel Case Directive

If the synthesis directive value includes parallel, the case statement is interpreted to mean that all the case labels have equal priority of matching the case expression. The optimizer uses this information to avoid building a decoder to decode for 2n alternatives where n is the size (in bits) of the case expression. The optimizer builds a parallel decoding logic instead of priority encoder logic to drive the select lines for the multiplexer.

The following model shows the parallel case synthesis directive:

case (1’b1) // ambit synthesis case = parallel cc[0] : cntr = 0 ;

cc[1] : cntr = data_in ; cc[2] : cntr = cntr - 1 ; cc[3] : cntr = cntr + 1 ;

endcase

During simulation, if the case expression matches more than one case label, the logic corresponding to each case label will be enabled. This causes the results to differ between

RTL simulation and netlist simulation. These situations may also occur if you use casex or casez statements to mask certain combinations. The RTL simulation will execute the procedural assignment corresponding to the first case label match, whereas the gate-level simulation will enable the logic for all the matching case labels. Therefore, you should ensure that only one case label is matched in the case statement before using the parallel case directive.