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■Hierarchical VHDL Designs on page 83

■VHDL-Related Commands and Globals on page 86

Modeling Combinational Logic

BuildGates synthesis software synthesizes combinational logic to implement a variable or signal under any of the following conditions:

■The variable or signal is unconditionally assigned a value before it is used and whenever any of the signals in the right-hand side expression change.

For example, combinational logic is synthesized to generate signal z in the model below:

■The variable or signal is conditionally assigned a value under all possible conditions whenever any of the signals in the right-hand side expression change. For example, combinational logic is synthesized to generate signal z in the model below:

Register Inferencing

A register is a level sensitive (latch) or edge-triggered (flip-flop) memory element. Ambit

BuildGates synthesis infers registers from the syntax of the HDL and generates a sequential element table that reports the number and type of memory elements inferred for the model synthesized by the do_build_generic command.

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The following sections describe how registers are inferred:

■Latch Inference on page 52

■Flip-Flop Inferencing on page 53

Specifying Clock Edges on page 54

Latch Inference

Ambit BuildGates synthesis infers a latch for a variable that is incompletely assigned, and that is updated whenever any of the variables that contribute to its value change (see example below).

Signal dout is modified when signal en is high. The model does not specify what happens when en is low (or unknown). The default behavior implied by VHDL is that the signal dout retains its previous value. The software infers a latch to implement the signal dout.

In VHDL’93, the same latch could be inferred by using a concurrent conditional signal assignment:

dout <= din when (en = '1');

Such an incomplete assignment is not possible in VHDL’87 since the conditional signal assignment in VHDL’87 is required to have an else clause.

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Flip-Flop Inferencing

When a process is triggered by a rising edge or a falling edge transition on a signal (typically a clock signal), the variable or signal on the left-hand side of a procedural assignment is inferred as a flip-flop. This is shown in the model below:

A rising-edge-triggered D-type flip-flop is inferred when data input is connected to din, clock input is connected to clk, and output is connected to dout.

In VHDL’93, the same flip-flop could be modeled by using a concurrent conditional signal assignment:

dout <= din when rising_edge(clk);

Note: This model uses the standard rising_edge function (defined in packages

IEEE.STD_LOGIC_1164 and IEEE.NUMERIC_BIT) to specify a positive edge on signal clk.

Synchronous set and reset On a Flip-Flop

A flip-flop with synchronous set and reset connections is synthesized when the model is written as follows:

process(clk) begin

if clk'event and clk = '1' then if set = '1' then

dout <= '1';

elsif reset = '1' then dout <= '0';

else

dout <= din; end if;

end if; end process;

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The process is triggered only on the rising edge of clk, but the assignment to dout is controlled by set and reset signals; dout is assigned the value of din only when set and reset are inactive.

Only single-bit set and reset signals are supported. See Synthesis Directives on page 59 for more information on controlling the set and reset connections for a flip-flop.

Asynchronous set and reset On a Flip-Flop

A flip-flop with asynchronous set and reset connections is synthesized when the model is written as follows:

process(clk, set, reset) begin

if set = '1' then dout <= '1';

elsif reset = '1' then dout <= '0';

elsif clk'event and clk = '1' then dout <= din;

end if; end process;

The process is triggered when a rising edge is detected on clk or a change is detected on set or reset. If set or reset is active low, then the condition in the if statement should be negated.

process(clk, set, ...)

begin

if set = '0' then

dout <= '1';

...

Only single-bit controls are accepted for set and reset. See Synthesis Directives on page 59 for more information on controlling the set and reset connections for a flip-flop.

Specifying Clock Edges

Clock edges can be specified for flip-flops in the context of if, wait, and conditional signal assignment (VHDL’93 mode only) statements. The following three statements are equivalent:

■Using an if statement:

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process (clk) begin

if (clk'event and clk = '1') then dout <= din;

end if; end p

■Using a wait statement:

process begin

wait until (clk'event and clk = '1'); dout <= din;

end process;

■Using a conditional signal assignment statement in VHDL’93:

dout <= din when (clk'event and clk = '1');

For each of the cases above, clock signals can be of bit, boolean, std_ulogic and std_logic types. The clock edge expression for a signal clk can be specified in several ways. The rising edge of the clock signal can take the following forms:

■For bit clock signals:

clk'event and clk = '1'

not clk'stable and clk = '1'

■For boolean clock signals:

clk'event and clk = TRUE

not clk'stable and clk = TRUE

■For std_ulogic and std_logic clock signals:

rising_edge(clk)

clk'event and clk = '1'

not clk'stable and clk = '1'

The falling edge of the clock signal can specified in one of the following ways:

■For bit clock signals:

clk'event and clk = '0'

not clk'stable and clk = '0'

■For boolean clock signals:

clk'event and clk = FALSE

not clk'stable and clk = FALSE

■For std_ulogic and std_logic clock signals: