Envisia HDL Modeling Reference

Verilog Constructs

Fully Supported Constructs

Fully supported constructs can be used unconditionally in describing a model. These include the basic module declaration, instantiation, use of reg and wire data types, continuous assignments, always procedural block, and many of the procedural statements.

Declarations

The following module, task, function, and data type declarations are fully supported.

■module, macromodule declarations

■function, endfunction

■task, endtask

■input, output, inout port declaration, memory

■wire, wand, wor, tri, triand, trior, supply0, supply1

■integer, reg

■parameter

■local variables

Operators and Expressions

Table A-1 lists the fully supported operators (and expressions comprised of these operators with legal operands).

Table A-1 Operators and Expressions

Envisia HDL Modeling Reference

Verilog Constructs

Table A-1 Operators and Expressions, continued

Legal operands include:

■reg, integer and wire data types

■Parameters

■On wire and reg, for bit-select and for part-select in cases of constant MSB and LSB specifiers

■Sized and unsized constants in b, o, d, h bases (both unsigned and signed, as indicated by an upper or lower case “s,” for example: 4’sb1010)

■Signed constant (s or S)

■Use of x, z, ? in constants

Structural Statements

The following structural statements are fully supported.

■assign—continuous assignments

■module instantiation—named and ordered port connections

■parameter override—on module instantiation