Envisia HDL Modeling Reference

HDL Synthesis Overview

The instance I1 of FOO in entity TOP_VHDL is linked with the Verilog module foo (since foo and FOO are identical from a case-insensitive point of view). The instance, inst1 of FOO, in module TOP_VERILOG is not linked to foo (since a Verilog instantiation requires an exact name match).

Querying the HDL Design Pool

Design data is often organized into tens or even hundreds of HDL files. It is very useful to investigate the design hierarchy right after the HDL files are read into BuildGates synthesis, without first generating a generic netlist using do_build_generic.

BuildGates synthesis provides several commands that allow you to query the entire pool of HDL designs that have been read in using read_vhdl or read_verilog. Queries provide various useful information, including: determining which subtrees in the design hierarchy need to be synthesized and generating Makefile-like scripts for managing the design’s generic build and optimization steps.

To illustrate these commands (which are defined in the following sections), consider the following VHDL design that consists of three modules: TOP, BOT, and BOTG. Assume that the design below is in a VHDL file called design.vhd that has been read in using the read_vhdl command:

ac_shell> read_vhdl design.vhd

Entity BOTG is

generic (WIDTH : natural := 1);

port (O: out bit_vector(WIDTH-1 downto 0)); end;

Architecture A of BOTG is begin

O <= (others => ’1’); end;

Entity BOT is

port (O: out integer); end;

Architecture A of BOT is begin

O <= 25; end;

Envisia HDL Modeling Reference

HDL Synthesis Overview

Entity TOP is

port (O8: out bit_vector(7 downto 0); O1: out integer);

end;

Architecture A of TOP is begin

I1 : entity work.BOT port map (O1);

I8 : entity work.BOTG generic map (8) port map (O8); end;

Using get_hdl_top_level Command

The get_hdl_top_level command displays a list containing the names of all top level designs (designs that are not instantiated by any other design). From the example above, the command:

ac_shell> get_hdl_top_level

yields the following output.

TOP

Using get_hdl_hierarchy Command

The get_hdl_hierarchy command displays the design hierarchy. For each design, the command lists the names of the designs that are instantiated within and whether or not the instantiations are parameterized (using parameters in Verilog or generics in VHDL).

From the VHDL example above, the command:

ac_shell> get_hdl_hierarchy

yields the following output.

{TOP {{BOT n} {BOTG p}}} {BOT {}} {BOTG {}}

The output indicates that TOP instantiates both BOT (n represents a non-parameterized instantiation) and BOTG (p indicates a parameterized instantiation, since design BOTG contains generics). BOT and BOTG do not instantiate any other designs.

To obtain the hierarchy for a specific design, specify the module, for example:

ac_shell> get_hdl_hierarchy TOP

yields the following output.

{TOP {{BOT n} {BOTG p}}}