Envisia HDL Modeling Reference

HDL Synthesis Overview

instantiations. This option allows verification of the generic or mapped netlists without requiring any simulation models of the individual cells that are used.

Synthesizing Mixed VHDL/Verilog Designs

BuildGates synthesis allows you to synthesize VHDL and Verilog designs in the same session. No special attributes or synthesis directives are needed for mixed VHDL/Verilog synthesis.

When using mixed VHDL and Verilog instantiations, the following constraints apply:

■Component instances in a Verilog module are resolved if a module or technology cell with the exact name is found. For example, an instance of a module named foo can be resolved only with another VHDL or Verilog module named foo.

■Component instances in a VHDL module are resolved in a case-insensitive manner. For example, an instance of a module named foo in a VHDL module may be linked with other VHDL and Verilog modules named FOO, or Foo and so on. An error occurs if there are multiple modules whose names match foo in a case-insensitive manner.

In the example below, when reading VHDL and Verilog modules, each of the following modules instantiate FOO.

For VHDL:

entity TOP_VHDL is

...

I1 : FOO port map(...); -- linked with "foo" end;

For Verilog:

module TOP_VERILOG (...);

...

FOO inst1 (...); // not linked with "foo" endmodule

For Verilog:

module foo (...);

...

endmodule