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Finite State Machine Structure and Optimization

NEXT_STATE <= green; when green => data <= "11";

NEXT_STATE <= red;

when yellow => data <= "00"; NEXT_STATE <= red;

end case;

end process next_state_p; end architecture rtl;

VHDL FSM Directives

When a FSM is described, information pertaining to the encoding and optimization of the state assignments can be included in the source as attributes on the state signal or variable.

VHDL state_vector Directive

The state_vector synthesis directive enables you to specify the state vector and to specify the method of encoding and optimizing the FSM. Refer to Verilog state_vector Directive and Table 4-1 for more information about state_vector syntax and state_vector encoding options.

FSM Coding Styles

This section provides information about the coding style you should use when creating FSMs. The following coding styles are recommended to improve the quality of implementation and optimization on an FSM. When creating FSMs in BuildGates synthesis, follow these coding style rules:

■Code one FSM per module

■Keep extraneous logic in the FSM to a minimum

Remove all unused inputs and outputs and any logic that does not affect or depend on the FSM and associated logic.

■Code the design so that the FSM can be reset to a desired state

The behavior of the FSM is valid only after the reset has taken place. If the first operating cycle of the FSM produces output values that are important, or if these output values can only be initialized by a default assignment (which may be deleted during optimization with the -reachable option), the outputs of the FSM should also be set to desired values in the reset block.

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Example—RTL that shows how output initialization may be lost

always @ (state or reset) begin out=2’b00;

if (reset) begin next_state = STATE0; end

begin

case (state) STATE0: begin

next_state = STATE1; out = out+1;

end STATE1: begin

next_state = STATE2; out = out-1;

end STATE2: begin

next_state = STATE0 out = out+2;

end default: begin

next_state = STATE0; end

endcase end end

The code above shows the default value of out as 00. If the -reachable flag is set, the default case is optimized and out assumes the value 2’bxx (unknown).

Using the -reachable Option

To remove the default value of out during optimization, use the following Cadence pragma:

//ambit synthesis state_vector state_reg -reachable

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When the simulation begins, the value of out is always 2’bxx. Note that the simulator interprets the default value to be 2’b00 in the RTL.

Avoiding a Simulation Mismatch

To avoid a simulation mismatch, change the reset block as follows:

if (reset) begin

next_state = STATE0;

out = 2b’00;

end

■Include as much don’t care information as possible in the design.

If the transitions from the invalid states (represented by the default case) are unimportant, then the state and output values can be set to don’t care values. The recommended method for implementing this is as follows:

default: next_state <= 4’bxxxx;

out1 <= 2’bxx;

Using this method adds flexibility when optimizing the netlist and all invalid (unreachable) states of the FSM can be treated as don’t cares. This is achieveable using the -reachable option (see Using the -reachable Option on page 100).

If design methodology constraints prohibit the use of the previous method, you can use a specific valid state, such as the reset state of the FSM or any other valid state and a constant output value for outputs.

default: next_state <= 4’b0000;//reset state of the machine

out1 <= 2’b01;

Important

The following coding style for the default case is not recommended.

default:next_state <=current_state;

[out1 <= func(current_state)]

The full case pragma is ignored if the default clause is present. Note that you can simulate the full case directive by using the -reachable option. (see Using the - reachable Option on page 100).

■Assign output values explicitly, whenever possible.

The following is an example of very compact code. The variable out is 0 in STATE0, but is a don’t care in STATE1 and also in the default clause.

begin

out = 1’b0;

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case (state) STATE0: begin

next_state = STATE1; end

STATE1: begin

next_state = STATE2; end

STATE2: begin

next_state = STATE0 out = 1’b1;

end default: begin

next_state = STATE0; end

endcase end

By implementing a more detailed coding style, a more optimized design can be specified as follows:

case (state) STATE0: begin

next_state = STATE1; out = 1’b0;

end STATE1: begin

next_state = STATE2; out = 1’bx;

end STATE2: begin

next_state = STATE0 out = 1’b1;

end default: begin

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Finite State Machine Structure and Optimization

next_state = STATE0;

out = 1’bx;

end

endcase

■Be explicit when assigning the outputs in each state of the FSM.

Outputs that are not specified completely are not handled by the FSM flow in BuildGates synthesis. In the code example below, out is not specified completely and causes the

FSM extraction from the HDL to fail. Note that this design would be treated like normal

HDL and synthesized outside the FSM flow.

case (state) STATE0: begin

next_state = STATE1; out = 1’b0;

end STATE1: begin

next_state = STATE0; end

default: begin

next_state = STATE0; out = 1’bx;

end endcase

If out is to retain its value in STATE1, use another variable to store the previous value of out and assign it explicitly to out.

If the output is a don’t care for some conditions, it should be driven unknown (x).

BuildGates synthesis uses all don’t care information when optimizing the logic.

Assigning the output to a default value prior to the case statement ensures that the output is specified for all possible state and input combinations. This avoids unexpected latch inference on the output. Latch inferencing prevents the software from extracting the FSM. You can simplify the code by specifying a default value that may be overridden only when necessary. The default value may be 1, 0, or x.

It is best to set the default value to the most frequently occurring value at that output or to a don’t care whenever possible. BuildGates synthesis software performs an onset as well as an offset synthesis and picks the best option (with a possible inverter) for implementing the next state and the output logic of an FSM.

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■Use the -reachable and -encoding area options together to achieve the best optimization results.

Using the two options together provides the best results. In cases where the FSM is on the critical path and timing is very critical, using -encoding timing or

-encoding one_hot is recommended.

Verification of Synthesized FSMs

This section provides you with information to verify the logic correctness of the synthesized

FSMs by using the various workarounds to solve these problems. Most design environments provide either a simulation-based or equivalence-checking-based verification flow. BuildGates synthesis addresses the following two flows independently:

■Equivalence-Checking-Based Verification Flow on page 104

■Simulation-Based Verification Flow on page 106

Equivalence-Checking-Based Verification Flow

FSM synthesis uses a suite of sequential optimization techniques (such as Unreachable State Removal, State Assignment or Re-Encoding, and State Minimization). The netlist resulting from synthesizing your FSM design will not be combinationally equivalent to the original HDL description. Mismatches between the RTL of the FSM and its synthesized netlist are reported if you use combinational equivalence checkers.

Workarounds to Avoid Mismatches in a Equivalence-Checking Environment

To avoid mismatches between the RTL of the FSM and its synthesized netlist, use one of the following workarounds:

■Avoid Using Any Sequential Optimizations on page 104

■Use Only the -reachable Sequential Optimization on page 105

■Do Not Specify Any Sequential Optimizations with the State Vector Pragma in the HDL of the FSM on page 105

Avoid Using Any Sequential Optimizations

This approach avoids using any sequential optimizations. The default clause of the case statement that defines the state machine must have a restricted structure.

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The default clause represents the action taken by the state machine upon reaching an invalid state. The designer however is not generally interested in the invalid states, so a reset signal is used to set the FSM to a reset state so that the machine can start operating. Using this approach, the FSM never enters the default case (invalid states). Note that constraints should not be imposed on invalid states.

Coding the Default Clause with a Restricted Structure

To code the default clause of the case statement that defines the state machine with a restricted structure, model your code as follows:

default: next_state <= 4’bxxxx;

out <= 2’bxx;

The benefit of using this approach provides BuildGates synthesis software with added flexibility when optimizing the netlist and all invalid (unreachable) states of the FSM can be treated as don’t cares. Another benefit of using this approach is that you avoid generating any false counter examples (where the state vector component is invalid).

Use Only the -reachable Sequential Optimization

This approach uses only the sequential optimization with the -reachable option.

Examine the output from the equivalence checker, which is essentially a value assignment (difference vector), in terms of the inputs and latches of the design that violate the expected outcome.

Viewing the Valid States

To view the set of valid states, do the following:

In ac_shell (or pks_shell if applicable), enter the following command:

report_fsm -state

If the state register component of the difference vectors (generated as counterexamples) belongs to the invalid or unreachable states, then it’s a false alarm and can be ignored.

Do Not Specify Any Sequential Optimizations with the State Vector Pragma in the HDL of the FSM

This approach does not specify any sequential optimizations with the state vector pragma in the HDL of the FSM (sequential optimizations such as Unreachable State Removal, State

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Assignment or Re-Encoding, and State Minimization). There is a little room for optimization using the do_build_generic command with the -extract_fsm option.

Simulation-Based Verification Flow

Most design environments have the simulation environment set up to assert the reset signal, which initializes a subset of the memory elements in the full design. The FSM state register is also reset to the desired start state by such a reset line. The importance of being able to reset the state register is emphasized in Verilog and VHDL FSM Directives on page 95.

After the simulation begins, the FSM enters the start state and always operates in the set of valid states (if the FSM is well designed). As the simulation environment examines the input and output behavior of the FSM (not it’s state register value), sequential optimizations (such as State Assignment or Re-Encoding and State Minimization) are permitted on the state machine.

Additionally, as the reset signal always transitions the FSM to a valid state, the simulation environment does not have to consider transitions from invalid states (represented by the default case statement). The interpretation of invalid states as don’t cares causes no verification problems and provides the desired flexibility. In the following example, equivalence checking fails to verify the synthesized FSM, whereas a simulator succeeds.

module fsm1 (clk, out, reset, state); input clk, reset;

output [1:0] out; output [1:0] state;

parameter [1:0] // ambit synthesis enum state_info STATE0 = 2’b00,

STATE1 = 2’b01,

STATE2 = 2’b10;

reg [1:0] /* ambit synthesis enum state_info */ state;

reg [1:0] /* ambit synthesis enum state_info */ next_state; reg [1:0] out;

// ambit synthesis state_vector state -reachable always @ (posedge clk)

state <= next_state;

always @ (state or reset) begin if (reset) begin

out = 2’b01; next_state = STATE0;

end

else begin

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case (state) STATE0: begin

next_state = STATE1; out = state;

end STATE1: begin

next_state = STATE2; out = state;

end STATE2: begin

next_state = STATE0 out = state;

end default: begin

next_state = STATE0; out = 2’b11;

end endcase end

end

endmodule

Using the -reachable option, the default state (2’b11) is treated as a don’t care. The values of the next_state and the output out (specified in the default clause) will therefore not be honored. The synthesized netlist and the original netlist (using a combinational equivalence checker) will mismatch. The counter -example produced by the equivalence checker has its state bits set to 2’b11 (the invalid state that is treated as a don’t care).

In the simulation, the reset signal is asserted, causing the FSM to transition to STATE0. From STATE0, no simulation sequence exercises the invalid transitions, therefore treating the invalid state as a don’t care and causing no problems in the simulation.

Note that the simulation environment must be set up to pull up the reset beforehand so there is no mismatch for the simulation sequence prior to the event that asserts the reset.

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Workarounds to Avoid Mismatches in a Simulation Environment

To avoid mismatches between the RTL of the FSM and its synthesized netlist, use one of the following workarounds:

■Ignore the Simulation Vectors on page 108

■If Unknown Values Persist in the Simulation Output on page 108

■Do Not Use the -reachable Option on page 109

Ignore the Simulation Vectors

This approach ignores the simulation vectors prior to the reset being pulled up; the FSM’s desired behavior only starts after the reset.

If Unknown Values Persist in the Simulation Output

This approach states that if x (unknown) values persist in the simulation output of the synthesized design (but not in the RTL simulation) after the reset is asserted, there is most likely a problem in the RTL design that needs to be fixed and not a bug in the synthesis. The x values usually die a few cycles after the reset, after which the synthesized netlist behaves identically to the RTL design.

Example—FSM where x Value Persists During Simulation

always @ (state or reset) begin out=2’b00;

begin case (state) STATE0:

begin

next_state = STATE1; out = out+1;

end STATE1: begin

next_state = STATE2; out = out-1;

end STATE2: begin

next_state = STATE0

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out = out+2;

end

default:

begin

next_state = STATE0;

end endcase end

if (reset) begin next_state = STATE0;

end end

The code above shows the default value of out as 00. If the -reachable flag is set, the default case is optimized and the value of out is assumed to be 2’bxx. When the simulation starts, the value of out will always be 2’bxx (unknown). The problem with the design is that it does not initialize out in the reset block. The simulator interprets the default value of out as 2’b00 in the RTL, but BuildGates synthesis software removes it during optimization using the

-reachable option.

Do Not Use the -reachable Option

This approach does not use the -reachable option.

The results you obtain will not be as good, but the simulation should progress without any problems. This is similar to the workaround above, but is not recommended.