- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •HDL Synthesis Overview
- •HDL Synthesis Flow
- •Read Technology Libraries
- •Read Design Data
- •Build Generic Design
- •Save Generic Netlist
- •Synthesizing Mixed VHDL/Verilog Designs
- •Querying the HDL Design Pool
- •Using get_hdl_top_level Command
- •Using get_hdl_hierarchy Command
- •Using get_hdl_type Command
- •Building Generic Netlists from HDL
- •Multiple Top-Level Designs
- •Building Parameterized Designs
- •Verilog Modeling Styles
- •Modeling Combinational Logic
- •Register Inferencing
- •Latch Inference
- •Flip-Flop Inference
- •case Statements
- •Incomplete case Statement
- •Complete case Statement
- •Use of casex and casez Statements
- •for Statement
- •Synthesis Directives
- •Code Selection Directives
- •Architecture Selection Directive
- •case Statement Directives
- •Module Template Directive
- •Function and Task Mapping Directives
- •Set and Reset Synthesis Directives
- •Verilog Preprocessor Directives
- •Compiler Directives
- •The ‘for Compiler Directive
- •The ‘if Compiler Directive
- •The ‘eval Compiler Directive
- •The ‘{} Compiler Directive
- •Command Line Options
- •VPP Flag Attribute
- •Verilog-Related Commands and Globals
- •VHDL Modeling Style
- •Modeling Combinational Logic
- •Register Inferencing
- •Latch Inference
- •Flip-Flop Inferencing
- •Specifying Clock Edges
- •case Statement
- •Incomplete case Statement
- •Complete case Statement
- •for loop
- •Synthesis Directives
- •Code Selection Directives
- •Architecture Selection Directive
- •case Statement Directive
- •Enumeration Encoding Directive
- •Entity Template Directive
- •Function and Procedure Mapping Directives
- •Signed Type Directive
- •Resolution Function Directives
- •Type Conversion Directives
- •Set and Reset Synthesis Directives
- •Reading VHDL Designs
- •Using Arithmetic Packages From Other Vendors
- •Switching between VHDL’87 / VHDL’93
- •Reusing Previously Analyzed Entities
- •Modifying Case of VHDL Names
- •Writing VHDL Netlists
- •Selecting Bit-Level Representation
- •Selecting Between VHDL’87 and VHDL’93
- •Referring to VHDL Packages in Netlists
- •Writing Component Declarations
- •Hierarchical VHDL Designs
- •Component Instantiations and Bindings
- •Restrictions on Entities with Multiple Architectures
- •Precedence Rules for Architecture Selection
- •VHDL-Related Commands and Globals
- •Finite State Machine Overview
- •BuildGates Synthesis and Finite State Machines
- •Extracting the State Transition Table for the FSM
- •Viewing the State Transition Table for the FSM
- •FSM Optimization Features
- •Unreachable State Removal
- •State Assignment or Re-Encoding
- •State Minimization
- •Terminal State Check
- •Verilog and VHDL FSM Directives
- •Verilog FSM Directives
- •VHDL FSM Directives
- •FSM Coding Styles
- •Using the -reachable Option
- •Avoiding a Simulation Mismatch
- •EDIF Interface
- •Reading EDIF Designs
- •Writing EDIF Designs
- •Representing Power and Ground in EDIF
- •Net Representation for Power and Ground
- •Port Representation for Power and Ground
- •Instance Representation for Power and Ground
- •Verilog Constructs
- •Fully Supported Constructs
- •Declarations
- •Operators and Expressions
- •Partially Supported Constructs
- •Ignored Constructs
- •Unsupported Constructs
- •Summary of Verilog Constructs
- •VHDL Constructs
- •Notes on Supported Constructs
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Envisia HDL Modeling Reference |
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Preface |
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[ ] |
Brackets denote optional arguments. When used with OR-bars, |
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they enclose a list of choices from which you can choose one. |
{ } |
Braces are used to indicate that a choice is required from the list |
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of arguments separated by OR-bars. You must choose one from |
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the list. |
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{ argument1 | argument2 | argument3 } |
{ } |
Bold braces are used in Tcl commands to indicate that the |
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braces must be typed in literally. |
... |
Three dots (...) indicate that you can repeat the previous |
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argument. If the three dots are used with brackets (that is, |
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[argument]...), you can specify zero or more arguments. If |
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the three dots are used without brackets (argument...), you |
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must specify at least one argument, but can specify more. |
# |
The pound sign precedes comments in command files. |
About the Graphical User Interface
This section describes the conventions used for the BuildGates synthesis graphical user interface (GUI) commands and describes how to use the menus and forms in the BuildGates synthesis software.
Using Menus
The GUI commands are located on menus at the top of the window. They can take one of three forms.
CommandName |
A command name with no dots or arrow executes immediately. |
CommandName… |
A command name with three dots displays a form for choosing |
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options. |
CommandName -> |
A command name with a right arrow displays an additional menu |
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with more commands. Multiple layers of menus and commands |
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are presented in what are called command sequences, for |
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example: File – Import – LEF. In this example, you go to the File |
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menu, then the Import submenu, and, finally, the LEF command. |
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Preface |
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Using Forms |
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… |
A menu button that contains only three dots provides browsing |
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capability. When you select the browse button, a list of choices |
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appears. |
Ok |
The Ok button executes the command and closes the form. |
Cancel |
The Cancel button cancels the command and closes the form. |
Defaults |
The Defaults button displays default values for options on the |
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form. |
Apply |
The Apply button executes the command but does not close the |
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form. |
Help |
The Help button provides information about the command. |
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