Envisia HDL Modeling Reference

Finite State Machine Structure and Optimization

State Minimization

This optimization tells the software to perform a minimization on the FSM and validate it. Each state of an FSM typically corresponds to a unique behavior. In some cases, however, two or more equivalent states, having identical I/O behavior, may occur in a state machine. This can be a result of performance reasons (by the designer) or a bug in the design. If equivalent states are found in the design it may mean that the design has a bug. If you are confident that your design does not have any equivalent states, then you can ignore this option and save on runtime. You can invoke state minimization using the following Cadence pragma:

Terminal State Check

A terminal state check is always performed on the extracted FSM. A terminal state is a state of the FSM from which there are no outputs. A well designed state machine should never have a terminal state. If such a state is found in the FSM, it is included in the FSM report (see Viewing the State Transition Table for the FSM on page 92).

Verilog and VHDL FSM Directives

Verilog FSM Directives

When a finite state machine is described, much of the information related to its state encoding is not written in the Verilog HDL model. Two synthesis directives are provided to capture this information. These are the enum and the state_vector directives. Using these directives in your Verilog HDL description causes the FSM to be extracted and optimized when the -extract_fsm option is specified with the do_build_generic command, as follows:

do_build_generic -extract_fsm

Envisia HDL Modeling Reference

Finite State Machine Structure and Optimization

The directives are described in detail in the following section. For optimization examples, see FSM Optimization Features on page 92.

Enumeration Directive

The enum synthesis directive is used to enumerate state assignments and to bind the state assignments to the state vector. A name for the enumeration is defined using the directive. It is bound to the state vector when the state vector (current state and next state) is declared.

The following is the syntax for the enum synthesis directive:

// ambit synthesis enum enumeration_name

The example below shows how to use the enum synthesis directive to represent state vector values.

module myfsm (clk, out, reset); input clk, reset;

output [1:0] out;

parameter [1:0] // ambit synthesis enum state_info STATE0 = 2’b00,

STATE1 = 2’b01,

STATE2 = 2’b10,

reg [1:0] /* ambit synthesis enum state_info */ state;

reg [1:0] /* ambit synthesis enum state_info */ next_state; reg [1:0] out;

// ambit synthesis state_vector state -encoding one_hot always @ (posedge clk) begin

if (reset)

state = STATE0; else

state = next_state;

end

always @ (state or reset) begin case (state)

STATE0 : begin next_state = STATE1; out = 2’b01;

end

STATE1: begin next_state = STATE2; out = 2’b10;

end

Envisia HDL Modeling Reference

Finite State Machine Structure and Optimization

STATE2: begin next_state = STATE0; out = 2’b10;

end

default: begin //represents the unreachable (invalid) states of the FSM // next_state = STATE0;

out = 2’bxx; end

endcase end endmodule

Using the enum directive with parameter declarations results in each parameter being taken as an enumeration of the state. The enum directive is used to associate the state vector (state and next_state above) with the state assignments enumerated by the parameter declaration. A warning is generated if the FSM is extracted with more states than the parameters specified as state enumeration.

If the enum synthesis directive is specified with the state vector declaration but has no enumeration of state encoding, the valid state assignments are derived automatically from the model.

Verilog state_vector Directive

The state_vector synthesis directive enables you to specify the state vector and to specify the method of encoding and optimizing the FSM.

The syntax for the synthesis state_vector directive is:

// ambit synthesis state_vector sig state_vector_flag

where sig is the name of the signal representing the state vector. The state_vector_flag is defined using one or more of the following options:

■encoding [binary|gray|one_hot|random|input|output|combined | area |timing]

■minimize

■reachable

■preserve_state

■initial_state

The state_vector encoding options are defined in Table 4-1.

Envisia HDL Modeling Reference

Finite State Machine Structure and Optimization

The following example defines the Verilog state_vector directive.

library IEEE;

use IEEE.std_logic_1164.all; library ambit;

use ambit.attributes.all;

entity fsm is port (

clk, rst : in std_logic;

data : out std_logic_vector(1 downto 0) ); end entity fsm;

architecture rtl of fsm is

type COLOR is (red, blue, green, yellow);

signal STATE, NEXT_STATE : COLOR;

begin

state_p: process (clk, rst) begin

if (rst = ’1’) then STATE <= red;

elsif (rising_edge(clk)) then STATE <= NEXT_STATE;

end if;

end process state_p;

next_state_p: process(state)