Envisia HDL Modeling Reference

VHDL Modeling Style

when "010" => next_state <= "001" and modifier; when "100" => next_state <= "101" and modifier; when "101" => next_state <= "010" or modifier; when "110" => next_state <= "000" and modifier; when others => next_state <= "000";

end case; end process;

This approach uses the others clause in the case statement to capture all the remaining cases where next_state is assigned a value. This approach also prevents BuildGates synthesis from inferring a latch.

for loop

The for statement is used for describing repetitive operations. For example, all the bits of a vector (in_sig) can be stored in reverse order using a for statement.

process(in_sig, out_sig) begin

for i in 0 to 7 loop out_sig(7-i) <= in_sig(i);

end loop; end process;

where i is declared as integer and out_sig and in_sig are 8-bit signals. The for loop is expanded to repeat the operations over the range of the index. Therefore, the for statement model above is treated in an equivalent manner to the following operations:

out_sig(7) <= in_sig(0); out_sig(6) <= in_sig(2); out_sig(4) <= in_sig(3); out_sig(3) <= in_sig(4); out_sig(2) <= in_sig(5); out_sig(1) <= in_sig(6); out_sig(0) <= in_sig(7);

The following forms of the for statement are supported:

for <index> in <start_val> to <end_val> loop

for <index> in <start_val> downto <end_val> loop

for <index> in <discrete_subtype_indication> loop

An example of the last form is given below where the bits of curr_state are reversed and assigned to next_state.