
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •HDL Synthesis Overview
- •HDL Synthesis Flow
- •Read Technology Libraries
- •Read Design Data
- •Build Generic Design
- •Save Generic Netlist
- •Synthesizing Mixed VHDL/Verilog Designs
- •Querying the HDL Design Pool
- •Using get_hdl_top_level Command
- •Using get_hdl_hierarchy Command
- •Using get_hdl_type Command
- •Building Generic Netlists from HDL
- •Multiple Top-Level Designs
- •Building Parameterized Designs
- •Verilog Modeling Styles
- •Modeling Combinational Logic
- •Register Inferencing
- •Latch Inference
- •Flip-Flop Inference
- •case Statements
- •Incomplete case Statement
- •Complete case Statement
- •Use of casex and casez Statements
- •for Statement
- •Synthesis Directives
- •Code Selection Directives
- •Architecture Selection Directive
- •case Statement Directives
- •Module Template Directive
- •Function and Task Mapping Directives
- •Set and Reset Synthesis Directives
- •Verilog Preprocessor Directives
- •Compiler Directives
- •The ‘for Compiler Directive
- •The ‘if Compiler Directive
- •The ‘eval Compiler Directive
- •The ‘{} Compiler Directive
- •Command Line Options
- •VPP Flag Attribute
- •Verilog-Related Commands and Globals
- •VHDL Modeling Style
- •Modeling Combinational Logic
- •Register Inferencing
- •Latch Inference
- •Flip-Flop Inferencing
- •Specifying Clock Edges
- •case Statement
- •Incomplete case Statement
- •Complete case Statement
- •for loop
- •Synthesis Directives
- •Code Selection Directives
- •Architecture Selection Directive
- •case Statement Directive
- •Enumeration Encoding Directive
- •Entity Template Directive
- •Function and Procedure Mapping Directives
- •Signed Type Directive
- •Resolution Function Directives
- •Type Conversion Directives
- •Set and Reset Synthesis Directives
- •Reading VHDL Designs
- •Using Arithmetic Packages From Other Vendors
- •Switching between VHDL’87 / VHDL’93
- •Reusing Previously Analyzed Entities
- •Modifying Case of VHDL Names
- •Writing VHDL Netlists
- •Selecting Bit-Level Representation
- •Selecting Between VHDL’87 and VHDL’93
- •Referring to VHDL Packages in Netlists
- •Writing Component Declarations
- •Hierarchical VHDL Designs
- •Component Instantiations and Bindings
- •Restrictions on Entities with Multiple Architectures
- •Precedence Rules for Architecture Selection
- •VHDL-Related Commands and Globals
- •Finite State Machine Overview
- •BuildGates Synthesis and Finite State Machines
- •Extracting the State Transition Table for the FSM
- •Viewing the State Transition Table for the FSM
- •FSM Optimization Features
- •Unreachable State Removal
- •State Assignment or Re-Encoding
- •State Minimization
- •Terminal State Check
- •Verilog and VHDL FSM Directives
- •Verilog FSM Directives
- •VHDL FSM Directives
- •FSM Coding Styles
- •Using the -reachable Option
- •Avoiding a Simulation Mismatch
- •EDIF Interface
- •Reading EDIF Designs
- •Writing EDIF Designs
- •Representing Power and Ground in EDIF
- •Net Representation for Power and Ground
- •Port Representation for Power and Ground
- •Instance Representation for Power and Ground
- •Verilog Constructs
- •Fully Supported Constructs
- •Declarations
- •Operators and Expressions
- •Partially Supported Constructs
- •Ignored Constructs
- •Unsupported Constructs
- •Summary of Verilog Constructs
- •VHDL Constructs
- •Notes on Supported Constructs

Envisia HDL Modeling Reference
VHDL Modeling Style
when "010" => next_state <= "001" and modifier; when "100" => next_state <= "101" and modifier; when "101" => next_state <= "010" or modifier; when "110" => next_state <= "000" and modifier; when others => next_state <= "000";
end case; end process;
This approach uses the others clause in the case statement to capture all the remaining cases where next_state is assigned a value. This approach also prevents BuildGates synthesis from inferring a latch.
for loop
The for statement is used for describing repetitive operations. For example, all the bits of a vector (in_sig) can be stored in reverse order using a for statement.
process(in_sig, out_sig) begin
for i in 0 to 7 loop out_sig(7-i) <= in_sig(i);
end loop; end process;
where i is declared as integer and out_sig and in_sig are 8-bit signals. The for loop is expanded to repeat the operations over the range of the index. Therefore, the for statement model above is treated in an equivalent manner to the following operations:
out_sig(7) <= in_sig(0); out_sig(6) <= in_sig(2); out_sig(4) <= in_sig(3); out_sig(3) <= in_sig(4); out_sig(2) <= in_sig(5); out_sig(1) <= in_sig(6); out_sig(0) <= in_sig(7);
The following forms of the for statement are supported:
for <index> in <start_val> to <end_val> loop
for <index> in <start_val> downto <end_val> loop
for <index> in <discrete_subtype_indication> loop
An example of the last form is given below where the bits of curr_state are reversed and assigned to next_state.
September 2000 |
58 |
Product Version 4.0 |