Envisia HDL Modeling Reference

VHDL Modeling Style

falling_edge(clk)

clk'event and clk = '0'

not clk'stable and clk = '0'

All of these clock edge expressions can be used in if, wait, and conditional signal assignment statements.

In addition, the following expressions can be used in wait statements to specify rising and falling edges respectively:

case Statement

Using a case statement allows for multi-way branching in a functional description. When a case statement is used as a decoder to assign one of several different values to a variable, the logic can be implemented as combinational or sequential logic based on whether the signal or variable is assigned a value in branches of the case statement.

You can use the case statement in one of two ways when inferring a register.

■Incomplete case Statement on page 56

■Complete case Statement on page 57

Incomplete case Statement

When a case statement specifies only some of the values that the case expression can possibly have, a latch is inferred. For example, a state transition table may be modeled as follows:

signal curr_state, next_state, modifier:std_logic_vector(2 downto 0); process(curr_state, modifier)

begin

case curr_state is

when "000" => next_state <= "100" or modifier; when "001" => next_state <= "110" or modifier; when "010" => next_state <= "001" and modifier; when "100" => next_state <= "101" and modifier; when "101" => next_state <= "010" or modifier; when "110" => next_state <= "000" and modifier; when others => null;

Envisia HDL Modeling Reference

VHDL Modeling Style

end case;

end process;

The next_state signal is assigned a new value if curr_state is any one of the six values specified. For the other two possible states, the next_state signal retains its previous value. This behavior causes the software to infer a 3-bit latch for next_state.

Complete case Statement

If you do not want the software to infer a latch, the next_state signal must be assigned a value under all situations; next_state must have a default value.

Assigning a Default Value to next_state

There are two possible ways we can assign a default value to next_state.

■The first approach:

process(curr_state, modifier) begin

next_state <= "000"; case curr_state is

when "000" => next_state <= "100" or modifier; when "001" => next_state <= "110" or modifier; when "010" => next_state <= "001" and modifier; when "100" => next_state <= "101" and modifier; when "101" => next_state <= "010" or modifier; when "110" => next_state <= "000" and modifier; when others => null;

end case; end process;

The next_state signal is assigned a value unconditionally, then it is modified appropriately by the case statement. This approach prevents the software from inferring a latch.

■The second approach:

signal curr_state,next_state,modifier: std_logic_vector(2 downto 0);

process(curr_state, modifier) begin

case curr_state is

when "000" => next_state <= "100" or modifier; when "001" => next_state <= "110" or modifier;