Envisia HDL Modeling Reference

3

VHDL Modeling Style

This chapter describes the VHDL modeling style used with Ambit BuildGates synthesis tools.

Both VHDL’87 and VHDL’93 are supported, which adheres to the ANSI/IEEE standards on

VHDL language definition. Prior knowledge and experience of VHDL is assumed in this chapter. A summary of supported constructs can be found in the Appendix B, “” VHDL Constructs.

This chapter describes the impact that different modeling styles have on logic synthesis and netlist generation. Two models may simulate identically and describe the same behavior (functionality) of a design. However, the implementation of the two models through the logic synthesis process differs significantly in terms of their gate count (area), critical paths, and physical characteristics. This chapter also presents some of the constructs of VHDL’93 and how they affect synthesis. In addition to specific modeling styles and their impact on the netlist, a set of special comments, known as synthesis directives, are also described in this chapter.

The synthesizable subset of VHDL is based on the IEEE P1076.6 Standard for VHDL Register Transfer Level Synthesis. For more detail on the VHDL syntax and semantics, please refer to the following IEEE Standard VHDL Language Reference Manuals:

■ANSI/IEEE Std 1076-1987 (for VHDL’87)

■ANSI/IEEE Std 1076-1993 (for VHDL’93)

This chapter includes the following information:

■Modeling Combinational Logic on page 51

■Register Inferencing on page 51

■case Statement on page 56

■for loop on page 58

■Synthesis Directives on page 59

■Reading VHDL Designs on page 73

■Writing VHDL Netlists on page 81