Envisia HDL Modeling Reference

Verilog Modeling Styles

When you run read_verilog and do_build_generic, you get a report as shown below.

Verilog Preprocessor Directives

The following compiler directives are added through the Verilog Pre-Processor (VPP):

■`for

■`if

■`eval

■`{}

VPP also supports and interprets the following Verilog HDL compiler directives.

■`define

■`ifdef,

■`else,

■`endif

■`include

The remaining Verilog HDL compiler directives, when encountered in the source code, are passed on to the Verilog HDL parser as is, without any interpretation by VPP.

Compiler Directives

This section describes the compiler directives:

Envisia HDL Modeling Reference

Verilog Modeling Styles

The ‘for Compiler Directive

The `for compiler directive is a loop to define complex repetitive expressions and statements. The syntax of this directive is as follows:

‘for var = constant1 to constant2 step ?up | down? constant3

Verilog description

‘end

where var is the name of a variable; constant1, constant2, and constant3 are integer constants; and Verilog description is any legal Verilog syntax.

The variable var is visible only within the scope of this directive (between ‘for and ‘end). It can be referenced using ‘var. It can not be modified within the Verilog description. The initial value of var is set to constant1 for the first iteration and incremented (or decremented, if the keyword down is used) by constant3 on every iteration.

The iterations are terminated when the value of var is greater (less) than constant2. The Verilog description embedded within this directive is repeated for each iteration, substituting the current iteration value for the variable var if it is referenced within the

Verilog description.

In combination with the `if and `eval compiler directives (described below), this compiler directive can be very useful. It allows for VHDL type if-generate and for-generate capability to be supported in Verilog HDL. Refer to the model below.

`define BITS 5

`for i = `eval(`BITS-1) to 0 step down 1 `if (`i == 0)

halfadder U`i (a[`i],b[`i],s[`i],c[`i]); `else

fulladder U`i (a[`i],b[`i],c[`eval(`i-1)],s[`i],c[`i]); `endif

`end produces

fulladder U4 (a[4], b[4], c[3], s[4], c[4]); fulladder U3 (a[3], b[3], c[2], s[3], c[3]); fulladder U2 (a[2], b[2], c[1], s[2], c[2]); fulladder U1 (a[1], b[1], c[0], s[1], c[1]); halfadder U0 (a[0], b[0], s[0], c[0]);

The ‘for compiler directive may be nested in other compiler directives, including other ‘for compiler directives.

Envisia HDL Modeling Reference

Verilog Modeling Styles

The ‘if Compiler Directive

VPP expands the syntax of the `if compiler directive (Verilog HDL) to allow constant expressions using the following operators:

||

&&

==

!=

The syntax of this compiler directive is as follows:

‘if (expression)

verilog description

?‘else

verilog description?

‘endif

where expression is a constant expression composed of the legal operators listed above. For example,

`if ((`i == 0) || (`j == 1))

example i`i (a[`i], b[`j], c);

`else

example2 i`i (a[`eval(`i-1), b[`j], c);

`endif

The ‘eval Compiler Directive

VPP uses the `eval compiler directive to evaluate expressions involving defined macros and constants. The syntax for the `eval compiler directive is as follows:

‘eval(expression)

where expression is an expression with constant operands.

The operand can be either a constant number or a reference to a macro with a constant value.

The ‘{} Compiler Directive

Since Verilog gives no particular way to handle the building of complex macros using a combination of macros, VPP provides ‘{ABC} to evaluate a previously defined macro ABC.

For example, the following is not supported in Verilog HDL:

`define XYZ AND