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VHDL Constructs

\a+b\ \3state\ \type\ \(a&b)|c\

For more information about identifiers and extended identifiers, see the “Identifiers” section of the “Expressions” chapter.

Operators

logical

Logical operators are fully supported.

relational

Relational operators are fully supported.

addition

Concatenation and arithmetic operators are both fully supported.

signing

Signing operators are fully supported.

multiplying

The * (multiply) operator is fully supported. The / (division), mod, and rem operators are supported only when both operands are constant or when the right operand is a constant power of 2.

miscellaneous

The ** operator is supported only when both operands are constant or when the left operand is 2. The abs operator is fully supported.

operator overloading

Operator overloading is fully supported.

short-circuit operations

The short-circuit behavior of operators is not supported.

Shift and Rotate Operators

You can define shift and rotate operators for any one-dimensional array type whose element type is either of the predefined types, BIT or Boolean. The right operand is always of type integer. The type of the result of a shift operator is the same as the type of the left

VHDL Reference Guide

11-7

VHDL Reference Guide

operand. The shift and rotate operators are included in the list of

VHDL reserved words in the “VHDL Construct Support” section of this chapter. There is more information about the shift and rotate operators that numeric_std supports in the “Shift and Rotate Operators” section of the “Foundation Express Packages” chapter. The shift operators follow.

sll

Shift left logical

srl

Shift right logical

sla

Shift left arithmetic

sra

Shift right arithmetic

The rotate operators follow.

rol

Rotate left logical

ror

Rotate right logical

The following example illustrates the use of shift and rotate operators.

architecture arch of shft_op is

begin

 

 

a <= "01101";

 

q1

<= a sll 1;-- q1 = "11010"

q2

<= a srl 3;-- q2 = "00001"

q3

<= a rol 2;-- q3 = "10101"

q4

<= a ror 1;-- q4

= "10110"

q5

<= a sla 2;-- q5

= "10100"

q6

<= a sra 1;-- q6

= "00110"

end;

 

 

11-8

Xilinx Development System

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