- •About This Manual
- •Additional Resources
- •Manual Contents
- •Conventions
- •Typographical
- •Online Document
- •Using Foundation Express with VHDL
- •Hardware Description Languages
- •Typical Uses for HDLs
- •Advantages of HDLs
- •About VHDL
- •Foundation Express Design Process
- •Using Foundation Express to Compile a VHDL Design
- •Design Methodology
- •Design Descriptions
- •Entities
- •Entity Generic Specifications
- •Entity Port Specifications
- •Architecture
- •Declarations
- •Components
- •Concurrent Statements
- •Constant Declarations
- •Processes
- •Signal Declarations
- •Subprograms
- •Type Declarations
- •Examples of Architectures for NAND2 Entity
- •Configurations
- •Packages
- •Using a Package
- •Package Structure
- •Package Declarations
- •Package Body
- •Resolution Functions
- •Data Types
- •Type Overview
- •Enumeration Types
- •Enumeration Overloading
- •Enumeration Encoding
- •Enumeration Encoding Values
- •Integer Types
- •Array Types
- •Constrained Array
- •Unconstrained Array
- •Array Attributes
- •Record Types
- •Record Aggregates
- •Predefined VHDL Data Types
- •Data Type BOOLEAN
- •Data Type BIT
- •Data Type CHARACTER
- •Data Type INTEGER
- •Data Type NATURAL
- •Data Type POSITIVE
- •Data Type STRING
- •Data Type BIT_VECTOR
- •Unsupported Data Types
- •Physical Types
- •Floating-Point Types
- •Access Types
- •File Types
- •Express Data Types
- •Subtypes
- •Expressions
- •Overview
- •Operators
- •Logical Operators
- •Relational Operators
- •Adding Operators
- •Unary (Signed) Operators
- •Multiplying Operators
- •Miscellaneous Arithmetic Operators
- •Operands
- •Operand Bit-Width
- •Computable Operands
- •Aggregates
- •Attributes
- •Expressions
- •Function Calls
- •Identifiers
- •Indexed Names
- •Literals
- •Numeric Literals
- •Character Literals
- •Enumeration Literals
- •String Literals
- •Qualified Expressions
- •Records and Fields
- •Slice Names
- •Limitations on Null Slices
- •Limitations on Noncomputable Slices
- •Type Conversions
- •Sequential Statements
- •Assignment Statements and Targets
- •Simple Name Targets
- •Indexed Name Targets
- •Slice Targets
- •Field Targets
- •Aggregate Targets
- •Variable Assignment Statements
- •Signal Assignment Statements
- •Variable Assignment
- •Signal Assignment
- •if Statements
- •Evaluating Conditions
- •Using the if Statement to Infer Registers and Latches
- •case Statements
- •Using Different Expression Types
- •Invalid case Statements
- •loop Statements
- •Basic loop Statement
- •while...loop Statements
- •for...loop Statements
- •Steps in the Execution of a for...loop Statement
- •for...loop Statements and Arrays
- •next Statements
- •exit Statements
- •Subprograms
- •Subprogram Always a Combinatorial Circuit
- •Subprogram Declaration and Body
- •Subprogram Calls
- •Procedure Calls
- •Function Calls
- •return Statements
- •Procedures and Functions as Design Components
- •Example with Component Implication Directives
- •Example without Component Implication Directives
- •wait Statements
- •Inferring Synchronous Logic
- •Combinatorial Versus Sequential Processes
- •null Statements
- •Concurrent Statements
- •Overview
- •process Statements
- •Combinatorial Process Example
- •Sequential Process Example
- •Driving Signals
- •block Statements
- •Nested Blocks
- •Guarded Blocks
- •Concurrent Versions of Sequential Statements
- •Concurrent Procedure Calls
- •Concurrent Signal Assignments
- •Simple Concurrent Signal Assignments
- •Conditional Signal Assignments
- •Selected Signal Assignments
- •Component Instantiation Statements
- •Direct Instantiation
- •generate Statements
- •for...generate Statements
- •Steps in the Execution of a for...generate Statement
- •Common Usage of a for...generate Statement
- •if...generate Statements
- •Register and Three-State Inference
- •Register Inference
- •The Inference Report
- •Latch Inference Warnings
- •Controlling Register Inference
- •Inferring Latches
- •Inferring Set/Reset (SR) Latches
- •Inferring D Latches
- •Inferring Master-Slave Latches
- •Inferring Flip-Flops
- •Inferring D Flip-Flops
- •Inferring JK Flip-Flops
- •Inferring Toggle Flip-Flops
- •Getting the Best Results
- •Understanding Limitations of Register Inference
- •Three-State Inference
- •Reporting Three-State Inference
- •Controlling Three-State Inference
- •Inferring Three-State Drivers
- •Inferring a Simple Three-State Driver
- •Three-State Driver with Registered Enable
- •Three-State Driver Without Registered Enable
- •Writing Circuit Descriptions
- •How Statements Are Mapped to Logic
- •Design Structure
- •Adding Structure
- •Using Variables and Signals
- •Using Parentheses
- •Using Design Knowledge
- •Optimizing Arithmetic Expressions
- •Arranging Expression Trees for Minimum Delay
- •Sharing Common Subexpressions
- •Changing an Operator Bit-Width
- •Using State Information
- •Propagating Constants
- •Sharing Complex Operators
- •Asynchronous Designs
- •Don’t Care Inference
- •Using Don’t Care Default Values
- •Differences Between Simulation and Synthesis
- •Synthesis Issues
- •Feedback Paths and Latches
- •Fully Specified Variables
- •Asynchronous Behavior
- •Understanding Superset Issues and Error Checking
- •Foundation Express Directives
- •Notation for Foundation Express Directives
- •Foundation Express Directives
- •Translation Stop and Start Pragma Directives
- •synthesis_off and synthesis_on Directives
- •Resolution Function Directives
- •Component Implication Directives
- •Foundation Express Packages
- •std_logic_1164 Package
- •std_logic_arith Package
- •Using the Package
- •Modifying the Package
- •Data Types
- •UNSIGNED
- •SIGNED
- •Conversion Functions
- •Arithmetic Functions
- •Example 10-1: Binary Arithmetic Functions
- •Example 10-2: Unary Arithmetic Functions
- •Comparison Functions
- •Example 10-3: Ordering Functions
- •Example 10-4: Equality Functions
- •Shift Functions
- •ENUM_ENCODING Attribute
- •pragma built_in
- •Type Conversion
- •numeric_std Package
- •Understanding the Limitations of numeric_std package
- •Using the Package
- •Data Types
- •Conversion Functions
- •Resize Function
- •Arithmetic Functions
- •Comparison Functions
- •Defining Logical Operators Functions
- •Shift Functions
- •Rotate Functions
- •Shift and Rotate Operators
- •std_logic_misc Package
- •ATTRIBUTES Package
- •VHDL Constructs
- •VHDL Construct Support
- •Design Units
- •Data Types
- •Declarations
- •Specifications
- •Names
- •Identifiers and Extended Identifiers
- •Specifics of Identifiers
- •Specifics of Extended Identifiers
- •Operators
- •Shift and Rotate Operators
- •xnor Operator
- •Operands and Expressions
- •Sequential Statements
- •Concurrent Statements
- •Predefined Language Environment
- •VHDL Reserved Words
- •Examples
- •Moore Machine
- •Mealy Machine
- •Read-Only Memory
- •Waveform Generator
- •Smart Waveform Generator
- •Definable-Width Adder-Subtracter
- •Count Zeros—Combinatorial Version
- •Count Zeros—Sequential Version
- •Soft Drink Machine—State Machine Version
- •Soft Drink Machine—Count Nickels Version
- •Carry-Lookahead Adder
- •Carry Value Computations
- •Implementation
- •Serial-to-Parallel Converter—Counting Bits
- •Input Format
- •Implementation Details
- •Serial-to-Parallel Converter—Shifting Bits
- •Programmable Logic Arrays
VHDL Reference Guide
end;
end EXAMPLE;
For more information about subprograms, see the “Subprograms” section of the “Design Descriptions” chapter.
Subprogram Calls
Subprograms can have zero or more parameters. A subprogram declaration defines each parameter’s name, mode, and type. These are a subprogram’s formal parameters. When the subprogram is called, each formal parameter receives a value, termed the actual parameter. Each actual parameter’s value (of an appropriate type) can come from an expression, a variable, or a signal.
The mode of a parameter specifies whether the actual parameter can be the following.
•read from (mode in)
•written to (mode out)
•both read from and written to (mode inout).
Actual parameters that use mode out and mode inout must be variables or signals and include indexed names (A(1)) and slices (A(1 to 3)). They cannot be constants or expressions.
Procedures and functions are two kinds of subprograms.
•Procedures
Can have multiple parameters that use modes in, inout, and out Procedures do not return a value.
Procedures are used when you want to update some parameters (modes out and inout) or when you do not need a return value. An example might be a procedure with one inout bit vector parameter that inverted each bit in place.
•Functions
Can have multiple parameters, but only parameters that use mode in. Functions return their own function value. Part of a function definition specifies its return value type (also called the function type).
5-26 |
Xilinx Development System |
Sequential Statements
Use functions when you do not need to update the parameters, and you want a single return value. For example, the arithmetic function ABS returns the absolute value of its parameter.
Procedure Calls
A procedure call executes the named procedure with the given parameters. The syntax follows.
procedure_name [ ( [ name => ] expression
{ , [ name => ] expression } ) ] ;
expression: Each expression is called an actual parameter; expression is often just an identifier. If a name is present (positional notation), it is a formal parameter name associated with the actual parameter’s expression.
Formal parameters are matched to actual parameters by positional or named notation. A notation can mix named and positional notation, but positional parameters must precede named parameters.
A procedure call occurs in three steps.
1.Foundation Express assigns the values of the in and inout actual parameters to their associated formal parameters.
2.The procedure executes.
3.Foundation Express assigns the values of the inout and out formal parameters are assigned to the actual parameters.
In the synthesized circuit, the procedure’s actual inputs and outputs are wired to the procedure’s internal logic.
The following example shows a local procedure named SWAP that compares two elements of an array and exchanges these elements if they are out of order. SWAP is repeatedly called to sort an array of three numbers. The figure following the example illustrates the corresponding design.
library IEEE;
use IEEE.std_logic_1164.all;
package DATA_TYPES is
type DATA_ELEMENT is range 0 to 3;
type DATA_ARRAY is array (1 to 3) of DATA_ELEMENT; end DATA_TYPES;
VHDL Reference Guide |
5-27 |
VHDL Reference Guide
library IEEE;
use IEEEE.std_logic_1164.all; use WORK.DATA_TYPES.ALL;
entity SORT is
port(IN_ARRAY: in DATA_ARRAY; OUT_ARRAY: out DATA_ARRAY);
end SORT;
architecture EXAMPLE of SORT is begin
process(IN_ARRAY)
procedure SWAP(DATA: inout DATA_ARRAY; LOW, HIGH: in INTEGER) is
variable TEMP: DATA_ELEMENT; begin
if(DATA(LOW) > DATA(HIGH)) then -- Check -- data
TEMP := DATA(LOW);
DATA(LOW) := DATA(HIGH); -- Swap data DATA(HIGH) := TEMP;
end if; end SWAP;
variable MY_ARRAY: DATA_ARRAY;
begin
MY_ARRAY := IN_ARRAY; -- Read input to -- variable
-- Pair-wise sort SWAP(MY_ARRAY, 1, 2); -- Swap 1st and 2nd SWAP(MY_ARRAY, 2, 3); -- Swap 2nd and 3rd SWAP(MY_ARRAY, 1, 2); -- Swap 1st and 2nd
-- again
OUT_ARRAY <= MY_ARRAY; -- Write result to -- output
end process; end EXAMPLE;
Figure 5-9 Circuit Design for Procedure Call to Sort an Array
5-28 |
Xilinx Development System |
Sequential Statements
Function Calls
A function call executes a named function with the given parameter values. The value returned to an operator is the function’s return value. The syntax follows.
function_name ( [parameter_name =>] expression
{, [parameter_name =>] expression }) ;
•function_name is the name of a defined function.
•parameter_name, which is optional, is the name of a formal parameter as defined by the function. Each expression provides a value for its parameter and must evaluate to a type appropriate for that parameter.
You can specify parameter values in positional or named notation, as you can aggregate values.
In positional notation, the parameter_name -> construct is omitted. The first expression provides a value for the function’s first parameter, the second expression is for the second parameter, and so on.
In named notation, parameter_name -> is specified before an expression; the named parameter gets the value of that expression.
You can mix positional and named expressions in the same function call if you put all positional expressions before named parameter expressions.
The example below shows a simple function definition and two calls to that function.
function INVERT (A : BIT) return BIT is begin
return (not A); end;
...
process
variable V1, V2, V3: BIT; begin
V1 := ’1’;
V2 := INVERT (V1) xor 1;
V3 := INVERT (’0’); end process;
VHDL Reference Guide |
5-29 |
