VHDL Reference Guide

modeling switched transistors, because such a requirement is out of the scope of this package. Furthermore, mathematics, primitives, and timing standards are considered orthogonal issues as they relate to this package and are, therefore, beyond its scope.

The std_logic_1164 package has been updated with Foundation

Express synthesis directives.

To use this package in a VHDL source file, include the following lines at the beginning of the source file.

library IEEE;

use IEEE.std_logic_1164.all;

When you analyze your VHDL source file, Foundation Express automatically finds the IEEE library and the std_logic_1164 package. However, you must analyze the use packages not contained in the IEEE and Foundation Express libraries before processing a source file that uses them.

std_logic_arith Package

Functions defined in the std_logic_arith package provide conversion to and from the predefined VHDL data type INTEGER and arithmetic, comparison, and BOOLEAN operations. With this package, you can perform arithmetic operations and numeric comparisons on array data types. The package defines some arithmetic operators (+, - , *, and ABS) and the relational operators (<, >, <=, >=, =, and /=). (IEEE VHDL does not define arithmetic operators for arrays and defines the comparison operators in a manner inconsistent with an arithmetic interpretation of array values.)

The package also defines two major data types of its own;

UNSIGNED and SIGNED. Find details in the “Data Types” section of this chapter. The std_logic_arith package is legal VHDL; you can use it for both synthesis and simulation.

You can configure the std_logic_arith package to work on any array of single-bit types. You encode single-bit types in 1 bit with the ENUM_ENCODING attribute.

You can make the vector type (for example, std_logic_vector) synonymous with either SIGNED or UNSIGNED. This way, if you plan to use mostly UNSIGNED numbers, you do not need to convert your vector type to call UNSIGNED functions. The disadvantage of

Foundation Express Packages

making your vector type synonymous with either UNSIGNED or SIGNED is that it causes the standard VHDL comparison functions (=, /=, <, >, <=, and >=) to be redefined.

The table below shows that the standard comparison functions for BIT_VECTOR do not match the SIGNED and UNSIGNED functions.

Table 10-1 UNSIGNED, SIGNED, and BIT_VECTOR Comparison

Functions

Using the Package

To use this package in a VHDL source file, include the following lines at the beginning of the source file.

library IEEE;

use IEEE.std_logic_arith.all;

Modifying the Package

The std_logic_arith package is written in standard VHDL. You can modify or add to it. The appropriate hardware is then synthesized.

For example, to convert a vector of multivalued logic to an INTEGER, you can write the function shown in the following example. This MVL_TO_INTEGER function returns the integer value corresponding to the vector when the vector is interpreted as an unsigned (natural) number. If unknown values are in the vector, the return value is -1.

library IEEE;

use IEEE.std_logic_1164.all;

function MVL_TO_INTEGER(ARG : MVL_VECTOR) return INTEGER is

-- pragma built_in SYN_FEED_THRU