VHDL Reference Guide

end rtl;

TMP_Q_reg

Async-reset: RESET

Sync-toggle: TOGGLE

Figure 7-22 Toggle Flip-Flop with Enable and Asynchronous Reset

Getting the Best Results

This section provides tips for improving the results you achieve during flip-flop inference. The following topics are covered.

•Minimizing flip-flop count

•Correlating synthesis results with simulation results

Minimizing Flip-Flop Count HDL descriptions should build only as many flip-flops as the design requires.

Circuit Description Inferring Too Many Flip-Flops The following example shows a description that infers too many flip-flops. The inference report is shown following the example. The figure “Circuit with Six Inferred Flip-Flops” shows the inferred flip-flops.

Register and Three-State Inference

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity count is

port (CLK, RESET : in std_logic; AND_BITS, OR_BITS, XOR_BITS : out std_logic );

end count;

architecture rtl of count is begin

process

variable COUNT : std_logic_vector (2 downto 0); begin

wait until (CLK’event and CLK = ’1’); if (RESET = ’1’) then

COUNT <= ”000”; else

COUNT <= COUNT + 1; end if;

AND_BITS <= COUNT(2) and COUNT(1) and COUNT(0); OR_BITS <= COUNT(2) or COUNT(1) or COUNT(0); XOR_BITS <= COUNT(2) xor COUNT(1) xor COUNT(0);

end process;

end rtl;

The following example has only one process, which contains a wait statement and six output signals. Foundation Express infers six flipflops, one for each output signal in the process.

•COUNT(2:0) (three inferred flip-flops)

•AND_BITS (one inferred flip-flop)

•OR_BITS (one inferred flip-flop)

•XOR_BITS (one inferred flip-flop)

However, because the outputs AND_BITS, OR_BITS, and XOR_BITS depend solely on the value of variable COUNT, and variable COUNT is registered, these three outputs do not need to be registered. Therefore, assign AND_BITS, OR_BITS, and XOR_BITS within a process

VHDL Reference Guide

that does not have a wait statement (see the next section, “Circuit Description Inferring Correct Number of Flip-Flops”).

Figure 7-23 Circuit with Six Inferred Flip-Flops

Circuit Description Inferring Correct Number of Flip-Flops To avoid inferring extra flip-flops, assign the output signals from within a process that does not have a wait statement.

The following example shows a description with two processes, one with a wait statement and one without. The registered (synchronous) assignments are in the first process, which contains the wait statement. The other (asynchronous) assignments are in the second process. Signals communicate between the two processes.

This description style lets you choose the signals that are registered and those that are not. The inference report is shown following the example. The figure “Circuit with Three Inferred Flip-Flops” shows the resulting circuit.

Register and Three-State Inference

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity count is

port(CLK, RESET : in std_logic;

AND_BITS, OR_BITS, XOR_BITS : out std_logic); end count;

architecture rtl of count is

signal COUNT : std_logic_vector (2 downto 0); begin

reg : process begin

wait until (CLK’event and CLK = ’1’); if (RESET = ’1’) then

COUNT <= ”000”; else

COUNT <= COUNT + 1; end if;

end process reg;

combine : process(count) begin

AND_BITS <= COUNT(2) and COUNT(1) and COUNT(0); OR_BITS <= COUNT(2) or COUNT(1) or COUNT(0); XOR_BITS <= COUNT(2) xor COUNT(1) xor COUNT(0);

end process combine; end rtl;

COUNT_reg (width 3)

set/reset/toggle: none

VHDL Reference Guide

Figure 7-24 Circuit with Three Inferred Flip-Flops

This technique of separating combinatorial logic from registered or sequential logic in your design is useful when describing finite state machines. See these in the “Examples” appendix.

•“Moore Machine”

•“Mealy Machine”

•“Count Zeros—Sequential Version””

•“Soft Drink Machine—State Machine Version”

Correlating Synthesis Results with Simulation Results Using delay specifications with registered values can cause the simulation to behave differently from the logic Foundation Express synthesizes. For example, the description in the following example contains delay information that causes Foundation Express to synthesize a circuit that behaves unexpectedly (the post-synthesis simulation results do not match the pre-synthesis simulation results).

component flip_flop (D, CLK : in std_logic; Q : out std_logic );

end component;

process (A, CLK); signal B: std_logic;

begin

B <= A after 100ns;

F1: flip_flop port map (A, CLK, C),

F2: flip_flop port map (B, CLK, D); end process;

In the above example, B changes 100 nanoseconds after A changes. If the clock period is less than 100 nanoseconds, output D is one or