- •About This Manual
- •Additional Resources
- •Manual Contents
- •Conventions
- •Typographical
- •Online Document
- •Using Foundation Express with VHDL
- •Hardware Description Languages
- •Typical Uses for HDLs
- •Advantages of HDLs
- •About VHDL
- •Foundation Express Design Process
- •Using Foundation Express to Compile a VHDL Design
- •Design Methodology
- •Design Descriptions
- •Entities
- •Entity Generic Specifications
- •Entity Port Specifications
- •Architecture
- •Declarations
- •Components
- •Concurrent Statements
- •Constant Declarations
- •Processes
- •Signal Declarations
- •Subprograms
- •Type Declarations
- •Examples of Architectures for NAND2 Entity
- •Configurations
- •Packages
- •Using a Package
- •Package Structure
- •Package Declarations
- •Package Body
- •Resolution Functions
- •Data Types
- •Type Overview
- •Enumeration Types
- •Enumeration Overloading
- •Enumeration Encoding
- •Enumeration Encoding Values
- •Integer Types
- •Array Types
- •Constrained Array
- •Unconstrained Array
- •Array Attributes
- •Record Types
- •Record Aggregates
- •Predefined VHDL Data Types
- •Data Type BOOLEAN
- •Data Type BIT
- •Data Type CHARACTER
- •Data Type INTEGER
- •Data Type NATURAL
- •Data Type POSITIVE
- •Data Type STRING
- •Data Type BIT_VECTOR
- •Unsupported Data Types
- •Physical Types
- •Floating-Point Types
- •Access Types
- •File Types
- •Express Data Types
- •Subtypes
- •Expressions
- •Overview
- •Operators
- •Logical Operators
- •Relational Operators
- •Adding Operators
- •Unary (Signed) Operators
- •Multiplying Operators
- •Miscellaneous Arithmetic Operators
- •Operands
- •Operand Bit-Width
- •Computable Operands
- •Aggregates
- •Attributes
- •Expressions
- •Function Calls
- •Identifiers
- •Indexed Names
- •Literals
- •Numeric Literals
- •Character Literals
- •Enumeration Literals
- •String Literals
- •Qualified Expressions
- •Records and Fields
- •Slice Names
- •Limitations on Null Slices
- •Limitations on Noncomputable Slices
- •Type Conversions
- •Sequential Statements
- •Assignment Statements and Targets
- •Simple Name Targets
- •Indexed Name Targets
- •Slice Targets
- •Field Targets
- •Aggregate Targets
- •Variable Assignment Statements
- •Signal Assignment Statements
- •Variable Assignment
- •Signal Assignment
- •if Statements
- •Evaluating Conditions
- •Using the if Statement to Infer Registers and Latches
- •case Statements
- •Using Different Expression Types
- •Invalid case Statements
- •loop Statements
- •Basic loop Statement
- •while...loop Statements
- •for...loop Statements
- •Steps in the Execution of a for...loop Statement
- •for...loop Statements and Arrays
- •next Statements
- •exit Statements
- •Subprograms
- •Subprogram Always a Combinatorial Circuit
- •Subprogram Declaration and Body
- •Subprogram Calls
- •Procedure Calls
- •Function Calls
- •return Statements
- •Procedures and Functions as Design Components
- •Example with Component Implication Directives
- •Example without Component Implication Directives
- •wait Statements
- •Inferring Synchronous Logic
- •Combinatorial Versus Sequential Processes
- •null Statements
- •Concurrent Statements
- •Overview
- •process Statements
- •Combinatorial Process Example
- •Sequential Process Example
- •Driving Signals
- •block Statements
- •Nested Blocks
- •Guarded Blocks
- •Concurrent Versions of Sequential Statements
- •Concurrent Procedure Calls
- •Concurrent Signal Assignments
- •Simple Concurrent Signal Assignments
- •Conditional Signal Assignments
- •Selected Signal Assignments
- •Component Instantiation Statements
- •Direct Instantiation
- •generate Statements
- •for...generate Statements
- •Steps in the Execution of a for...generate Statement
- •Common Usage of a for...generate Statement
- •if...generate Statements
- •Register and Three-State Inference
- •Register Inference
- •The Inference Report
- •Latch Inference Warnings
- •Controlling Register Inference
- •Inferring Latches
- •Inferring Set/Reset (SR) Latches
- •Inferring D Latches
- •Inferring Master-Slave Latches
- •Inferring Flip-Flops
- •Inferring D Flip-Flops
- •Inferring JK Flip-Flops
- •Inferring Toggle Flip-Flops
- •Getting the Best Results
- •Understanding Limitations of Register Inference
- •Three-State Inference
- •Reporting Three-State Inference
- •Controlling Three-State Inference
- •Inferring Three-State Drivers
- •Inferring a Simple Three-State Driver
- •Three-State Driver with Registered Enable
- •Three-State Driver Without Registered Enable
- •Writing Circuit Descriptions
- •How Statements Are Mapped to Logic
- •Design Structure
- •Adding Structure
- •Using Variables and Signals
- •Using Parentheses
- •Using Design Knowledge
- •Optimizing Arithmetic Expressions
- •Arranging Expression Trees for Minimum Delay
- •Sharing Common Subexpressions
- •Changing an Operator Bit-Width
- •Using State Information
- •Propagating Constants
- •Sharing Complex Operators
- •Asynchronous Designs
- •Don’t Care Inference
- •Using Don’t Care Default Values
- •Differences Between Simulation and Synthesis
- •Synthesis Issues
- •Feedback Paths and Latches
- •Fully Specified Variables
- •Asynchronous Behavior
- •Understanding Superset Issues and Error Checking
- •Foundation Express Directives
- •Notation for Foundation Express Directives
- •Foundation Express Directives
- •Translation Stop and Start Pragma Directives
- •synthesis_off and synthesis_on Directives
- •Resolution Function Directives
- •Component Implication Directives
- •Foundation Express Packages
- •std_logic_1164 Package
- •std_logic_arith Package
- •Using the Package
- •Modifying the Package
- •Data Types
- •UNSIGNED
- •SIGNED
- •Conversion Functions
- •Arithmetic Functions
- •Example 10-1: Binary Arithmetic Functions
- •Example 10-2: Unary Arithmetic Functions
- •Comparison Functions
- •Example 10-3: Ordering Functions
- •Example 10-4: Equality Functions
- •Shift Functions
- •ENUM_ENCODING Attribute
- •pragma built_in
- •Type Conversion
- •numeric_std Package
- •Understanding the Limitations of numeric_std package
- •Using the Package
- •Data Types
- •Conversion Functions
- •Resize Function
- •Arithmetic Functions
- •Comparison Functions
- •Defining Logical Operators Functions
- •Shift Functions
- •Rotate Functions
- •Shift and Rotate Operators
- •std_logic_misc Package
- •ATTRIBUTES Package
- •VHDL Constructs
- •VHDL Construct Support
- •Design Units
- •Data Types
- •Declarations
- •Specifications
- •Names
- •Identifiers and Extended Identifiers
- •Specifics of Identifiers
- •Specifics of Extended Identifiers
- •Operators
- •Shift and Rotate Operators
- •xnor Operator
- •Operands and Expressions
- •Sequential Statements
- •Concurrent Statements
- •Predefined Language Environment
- •VHDL Reserved Words
- •Examples
- •Moore Machine
- •Mealy Machine
- •Read-Only Memory
- •Waveform Generator
- •Smart Waveform Generator
- •Definable-Width Adder-Subtracter
- •Count Zeros—Combinatorial Version
- •Count Zeros—Sequential Version
- •Soft Drink Machine—State Machine Version
- •Soft Drink Machine—Count Nickels Version
- •Carry-Lookahead Adder
- •Carry Value Computations
- •Implementation
- •Serial-to-Parallel Converter—Counting Bits
- •Input Format
- •Implementation Details
- •Serial-to-Parallel Converter—Shifting Bits
- •Programmable Logic Arrays
VHDL Reference Guide
package body package_name is { package_body_declarative_item }
end [ package_name ] ;
•package_name is the name of the associated package.
•package_body_declarative_item is any of the following statements.
•use clause
•subprogram declaration
•subprogram body
•type declaration
•subtype declaration
•constant declaration
The “Foundation Express Packages” chapter shows a package declaration and body example that comes with Foundation Express.
Resolution Functions
Resolution functions are used with signals that can be connected (wired together). For example, if two drivers directly connect to a signal, the resolution function determines whether the signal value is the AND, OR, or three-state function of the driving values.
Use resolution functions to assign the driving value when there are multiple drivers. For simulation, you can write an arbitrary function to resolve bus conflicts.
Note: A resolution function might change the value of a resolved signal, even if all drivers have the same value.
The resolution function for a signal is part of that signal’s subtype declaration. You create a resolved signal in four steps.
1.Declare the signal’s base type.
type SIGNAL_TYPE is ...
-- signal’s base type is SIGNAL_TYPE
2.Declare the resolution function.
function res_function (DATA: ARRAY_TYPE) return SIGNAL_TYPE is
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Design Descriptions
--declaration of the resolution function
--ARRAY_TYPE must be an unconstrained array of
--SIGNAL_TYPE
3.Declare the resolved signal’s subtype as a subtype of the base type, which includes the name of the resolution function.
subtype res_type is res_function SIGNAL_TYPE;
--name of the subtype is res_type
--name of function is res_function
--signal type is res_type (a subtype of SIGNAL_TYPE)
4.Declare resolved signals as resolved subtypes. signal resolved_signal_name:res_type;
--resolved_signal_name is a resolved signal
Foundation Express does not support arbitrary resolution functions. Only wired AND, wired OR, and three-state functions are allowed. Foundation Express requires that you mark all resolution functions with a special directive indicating the kind of resolution you want to perform.
Foundation Express considers the directive only when creating hardware. The body of the resolution function is parsed but ignored. Using unsupported VHDL constructs generates errors. (See the “VHDL Constructs” chapter.)
Do not connect signals that use different resolution functions. Foundation Express supports only one resolution function per network.
The three resolution function directives follow.
•synopsys resolution_method wired_and
•synopsys resolution_method wired_or
•synopsys resolution_method three_state
Pre-synthesis and post-synthesis simulation results might not match if the body of the resolution function the simulator uses does not match the directive the synthesizer uses.
The following example shows how to create and use a resolved signal and how to use Foundation Express directives for resolution functions. The signal’s base type is the predefined type BIT.
package RES_PACK is
function RES_FUNC(DATA: in BIT_VECTOR) return BIT;
VHDL Reference Guide |
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VHDL Reference Guide
subtype RESOLVED_BIT is RES_FUNC BIT; end;
package body RES_PACK is
function RES_FUNC(DATA: in BIT_VECTOR) return BIT is -- synopsis resolution_method wired_and
begin
--The code in this function is ignored by
--the program
--but parsed for correct VHDL syntax
for I in DATA’range loop if DATA(I) = ’0’ then
return ’0’; end if;
end loop; return ’1’;
end;
end;
use work.RES_PACK.all; entity WAND_VHDL is
port(X, Y: in BIT; Z: out RESOLVED_BIT); end WAND_VHDL;
architecture WAND_VHDL of WAND_VHDL is begin
Z <= X;
Z <= Y;
end WAND_VHDL;
The following figure shows the design.
AN2
X
Z
Y
X8641
Figure 2-2 Design Using Resolved Signal
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