Expressions

DOWN_VAR(0 to 1) -- Null slice (wrong direction) variable I: INTEGER range 0 to 7;

. . .

UP_VAR(I to I+1) -- Noncomputable slice

Limitations on Noncomputable Slices

IEEE VHDL does not allow noncomputable slices—slices whose range contains a noncomputable expression.

Type Conversions

Type conversions change an expression’s type. The syntax of a type conversion follows.

type_name (expression)

type_name is the name of a defined type. The expression must evaluate to a value of a type that can be converted into type type_name. The following conditions apply to type conversions.

•Type conversions can convert between integer types or between similar array types.

•Two array types are similar if they have the same length and if they have convertible or identical element types.

•Enumerated types cannot be converted.

The following example shows some type definitions and associated signal declarations, followed by valid and invalid type conversions.

type INT_1 is range 0 to 10; type INT_2 is range 0 to 20;

type ARRAY_1 is array(1 to 10) of INT_1; type ARRAY_2 is array(11 to 20) of INT_2;

subtype MY_BIT_VECTOR is BIT_VECTOR(1 to 10); type BIT_ARRAY_10 is array(11 to 20) of BIT; type BIT_ARRAY_20 is array(0 to 20) of BIT;

-- Legal type conversions

VHDL Reference Guide

INT_2(S_INT)

-- Integer type conversion

BIT_ARRAY_10(S_BIT_VEC)

--Similar array type conversion

--Illegal type conversions

BOOLEAN(S_BIT);

-- Can’t convert between enumerated types

INT_1(S_BIT);

-- Can’t convert enumerated types to other types

BIT_ARRAY_20(S_BIT_VEC);

-- Array lengths not equal

ARRAY_1(S_BIT_VEC);

-- Element types cannot be converted