VHDL Reference Guide
Async-set and Async-reset ==> Q: X
Sync-set and Sync-reset ==> Q: X
SET |
Q_OUT |
K |
J |
RESET |
CLK |
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Figure 7-19 JK Flip-Flop with Asynchronous Set and Reset
Inferring Toggle Flip-Flops
To infer toggle flip-flops, follow the coding style in the following examples. You must include asynchronous controls in the toggle flipflop description. Without them, you cannot initialize toggle flip-flops to a known state.
The following sections provide code examples, inference reports, and figures for these types of toggle flip-flops.
•Toggle flip-flop with asynchronous set
•Toggle flip-flop with asynchronous reset
•Toggle flip-flop with enable and asynchronous reset
Toggle Flip-Flop With Asynchronous Set The following example shows the VHDL template for a toggle flip-flop with asynchronous set. Foundation Express generates the inference report shown following the example, and the figure “Toggle Flip-Flop with Asynchronous Set” shows the flip-flop.
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Register and Three-State Inference
library IEEE, synopsys;
use IEEE.std_logic_1164.all; entity t_async_set is
port(SET, CLK : in std_logic; Q : out std_logic );
end t_async_set;
architecture rtl of t_async_set is signal TMP_Q : std_logic;
begin
infer: process (CLK, SET) begin if (SET = ’1’) then
TMP_Q <= ’1’;
elsif (CLK’event and CLK = ’1’) then TMP_Q <= not (TMP_Q);
end if;
Q <= TMP_Q;
end process infer; end rtl;
Register Name |
Type |
Width |
Bus |
MB |
AR |
AS |
SR |
SS |
ST |
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TMP_Q_reg |
Flip-flop |
1 |
- |
- |
N |
Y |
N |
N |
Y |
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TMP_Q_reg
Async-set: SET
Sync-toggle: true
Figure 7-20 Toggle Flip-Flop with Asynchronous Set
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VHDL Reference Guide
Toggle Flip-Flop With Asynchronous Reset The following example provides the VHDL template for a toggle flip-flop with asynchronous reset. The table following the example shows the inference report, and the figure following the report, “Toggle Flip-Flop with Asynchronous Reset,” shows the inferred flip-flop.
library IEEE ;
use IEEE.std_logic_1164.all;
entity t_async_reset is port(RESET, CLK : in std_logic;
Q : out std_logic ); end t_async_reset;
architecture rtl of t_async_reset is signal TMP_Q : std_logic;
begin
infer: process (CLK, RESET) begin if (RESET = ’1’) then
TMP_Q <= ’0’;
elsif (CLK’event and CLK = ’1’) then TMP_Q <= not (TMP_Q);
end if;
Q <= TMP_Q;
end process infer; end rtl;
Register Name |
Type |
Width |
Bus |
MB |
AR |
AS |
SR |
SS |
ST |
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TMP_Q_reg |
Flip-flop |
1 |
- |
- |
Y |
N |
N |
N |
Y |
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TMP_Q_reg
Async-reset: RESET
Sync-toggle: true
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Register and Three-State Inference
Figure 7-21 Toggle Flip-Flop with Asynchronous Reset
Toggle Flip-Flop With Enable and Asynchronous Reset The following example provides the VHDL template for a toggle flip-flop with an enable and an asynchronous reset. The flip-flop toggles only when the enable (TOGGLE signal) has a logic 1 value.
Foundation Express generates the inference report shown following the example, and the figure following the report, “Toggle Flip-Flop with Enable and Asynchronous Reset,” shows the inferred flip-flop.
library IEEE, synopsys;
use IEEE.std_logic_1164.all; use synopsys.attributes.all;
entity t_async_en_r is
port(RESET, TOGGLE, CLK : in std_logic; Q : out std_logic );
end t_async_en_r;
architecture rtl of t_async_en_r is signal TMP_Q : std_logic;
begin
infer: process (CLK, RESET) begin if (RESET = ’1’) then
TMP_Q <= ’0’;
elsif (CLK’event and CLK = ’1’) then if (TOGGLE = ’1’) then
TMP_Q <= not (TMP_Q); end if;
end if;
end process infer; Q <= TMP_Q;
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