VHDL Reference Guide
B when "01",
C when "10",
D when "11";
A
B
C 
Z
MUX41
D
CONTROL [0]
CONTROL [1]
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Figure 6-7 Circuit for Selected Signal Assignment
The following example shows a process equivalent to the previous example of selected signal assignment statement.
process(CONTROL, A, B, C, D) begin
case CONTROL is when 0 =>
Z <= A; when 1 => Z <= B; when 2 => Z <= C; when 3 => Z <= D;
end case; end process;
Component Instantiation Statements
The purpose of a component instantiation statement is to define a design hierarchy or build a netlist in VHDL by doing the following.
•Referencing a previously defined hardware component in the current design, at the current level of hierarchy
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Concurrent Statements
•Referencing components not defined in VHDL, such as the following.
•Components from a technology library (FPGA vendorspecific)
•Components defined in the Verilog hardware description language
The syntax follows.
instance_name : component_name port map (
[ port_name => ] expression
{, [ port_name => ] expression } );
•instance_name is the name of this instance of the component.
•component_name is the name of the component port map, which connects each port of this instance of component_name to a signal-valued expression in the current entity.
•port_name is the name of port.
•expression is the name of a signal, indexed name, slice name, or aggregate, to indicate the connection method for the component’s ports.
If expression is the VHDL reserved word open, the corresponding port is left unconnected.
You can map ports to signals by named or positional notation. You can include both named and positional connections in the port map, but you must put all positional connections before any named connections.
Note: For named association, the component port names must exactly match the declared component’s port names. For positional association, the actual port expressions must be in the same order as the declared component’s port order.
The example below shows a component declaration (a 2-input NAND gate) followed by three equivalent component instantiation statements.
component ND2
port(A, B: in BIT; C: out BIT); end component;
. . .
signal X, Y, Z: BIT;
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. . . |
|
|
U1: ND2 port map(X, Y, Z); |
-- positional |
|
U2: ND2 port map(A => X, C => Z, B => Y);-- |
named |
|
U3: ND2 port map(X, Y, C => Z); |
-- |
mixed |
The following example shows the component instantiation statement defining a simple netlist. The three instances, U1, U2, and U3, are instantiations of the 2-input NAND gate component declared in the example of component declaration and instantiations. The resulting circuit design is shown in the figure following the example.
signal TEMP_1, TEMP2: BIT;
. . .
U1: ND2 port map(A, B, TEMP_1); U2: ND2 port map(C, D, TEMP_2);
U3: ND2 port map(TEMP_1, TEMP_2, Z);
ND2
A
ND2
B
ND2 
Z
C
D 
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Figure 6-8 Simple Netlist Design
Direct Instantiation
A component instantiation statement
•Defines a subcomponent of the design entity in which it appears
•Associates signals or values with the ports of that subcomponent
•Associates values with generics of that subcomponent
The following two examples show the difference between a component instantiation statement and the more concise direct component instantiation statement.
ARCHITECTURE struct OF root IS COMPONENT leaf
PORT (
clk,data : in std_logic; Qout : out std_logic);
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