Chapter 1

Using Foundation Express with VHDL

Foundation Express translates a VHDL description to an internal gate-level equivalent format. This format is then optimized for a given FPGA technology.

This chapter discusses concepts that you need to work with VHDL. These concepts are covered in the following sections.

•“Hardware Description Languages”

•“About VHDL”

•“Foundation Express Design Process”

•“Using Foundation Express to Compile a VHDL Design”

•“Design Methodology”

The United States Department of Defense, as part of its Very High Speed Integrated Circuit (VHSIC) program, developed VHSIC HDL (VHDL) in 1982. VHDL describes the behavior, function, inputs, and outputs of a digital circuit design. VHDL is similar in style and syntax to modern programing languages, but includes many hard- ware-specific constructs.

Foundation Express reads and parses the supported VHDL syntax. The “VHDL Constructs” chapter lists all VHDL constructs and includes the level of support provided for each construct.

Hardware Description Languages

Hardware description languages (HDLs) are used to describe the architecture and behavior of discrete electronic systems.

HDLs were developed to deal with increasingly complex designs. An analogy is often made to the development of software description

VHDL Reference Guide

languages; from machine code (transistors and solder) to assembly language (netlists) to high-level languages (HDLs).

Top-down, HDL-based system design is most useful in large projects, where several designers or teams of designers are working concurrently. HDLs provide structured development. After major architectural decisions have been made and major components and their connections have been identified, work can proceed independently on subprojects.

Typical Uses for HDLs

HDLs typically support a mixed-level description, where structural or netlist constructs can be mixed with behavioral or algorithmic descriptions. With this mixed-level capability, you can describe system architectures at a high level of abstraction; then incrementally refine a design into a particular component-level or gate-level implementation. Alternatively, you can read an HDL design description into Foundation Express, then direct the compiler to synthesize a gate-level implementation automatically.

Advantages of HDLs

A design methodology that uses HDLs has several fundamental advantages over a traditional gate-level design methodology. Some of the advantages are listed below.

•You can verify design functionality early in the design process and immediately simulate a design written as an HDL description.

Design simulation at this higher level, before implementation at the gate level, allows you to test architectural and design decisions.

•Foundation Express synthesizes and optimizes logic so you can automatically convert a VHDL description to a gate-level implementation in a given technology.

This methodology eliminates the former gate-level design bottleneck and reduces circuit design time and errors introduced when a VHDL specification is hand-translated to gates. With Foundation Express logic optimization, you can automatically transform a synthesized design to a smaller and faster circuit. You can apply information gained from the synthesized and optimized