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Chapter 7

Register and Three-State Inference

Foundation Express infers registers (latches and flip-flops) and threestate cells. This chapter explains inference behavior and results in the following sections.

“Register Inference”

“Three-State Inference”

Register Inference

By inferring registers, you can use sequential logic in your designs and keep your designs technology-independent. A register is a simple, one-bit memory device, either a latch or a flip-flop. A latch is a level-sensitive memory device. A flip-flop is an edge-triggered memory device.

Foundation Express’ capability to infer registers supports coding styles other than those described in this chapter. However, for best results, do the following.

Restrict each always block to a single type of memory-element inferencing: latch, latch with asynchronous set or reset, flip-flop, flip-flop with asynchronous reset, or flip-flop with synchronous reset.

Use the templates provided in the “Inferring Latches” section and “Inferring Flip-Flops” section of this chapter.

The Inference Report

Foundation Express generates a general inference report when building a design. It provides the asynchronous set or reset, synchronous set or reset, and synchronous toggle conditions of each latch or

VHDL Reference Guide

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VHDL Reference Guide

flip-flop, expressed in Boolean formulas. The following example shows the inference report for a JK flip-flop.

Register Name

Type

Widt

Bus

MB

AR

AS

SR

SS

ST

 

 

h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q_reg

Flip-flop

1

-

-

N

N

Y

Y

N

 

 

 

 

 

 

 

 

 

 

Q_reg

Sync-reset: J’ K

Sync-set: J K’

Sync-toggle: J K

Sync-set and Sync-reset ==> Q: X

The inference report shows the following.

Y indicates that the flip-flop has a synchronous reset (SR) and a synchronous set (SS).

N indicates that the flip-flop does not have an asynchronous reset (AR), an asynchronous set (AS), or a synchronous toggle (ST).

In the inference report, the last section of the report lists the objects that control the synchronous reset and set conditions. In this example (Inference Report for a JK Flip-Flop), a synchronous reset occurs when J is low (logic 0) and K is high (logic 1). The last line of the report indicates the register output value when both the set and reset are active.

zero (0)—Indicates that the reset has priority and the output goes to logic 0

one (1)—Indicates that the set has priority and the output goes to logic 1

X—Indicates that there is no priority and that the output value is unstable

The “Inferring Latches” section and “Inferring Flip-Flops” section of this chapter provide inference reports for each register template. After you read a description in Foundation Express, check the inference report.

Latch Inference Warnings

Foundation Express generates a warning message when it infers a latch. The warning message is useful to verify that a combinatorial design does not contain memory components.

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Xilinx Development System

Register and Three-State Inference

Controlling Register Inference

Use directives to direct the type of sequential device you want inferred. The default is to implement the type of latch described in the HDL code. These attributes override this behavior.

The ATTRIBUTES package in the VHDL library defines the following attributes for controlling register inference.

async_set_reset

When this is set to TRUE on a signal, Foundation Express searches for a branch that uses the signal as a condition. Foundation Express then checks whether the branch contains an assignment to a constant value. If the branch does, the signal becomes an asynchronous reset or set.

Attach the async_set_reset attribute to 1-bit signals using the following syntax.

attribute async_set_reset of signal_name_list : signal is ”true”;

async_set_reset_local

Foundation Express treats listed signals in the specified process as if they have the async_set_reset attribute set to TRUE.

Attach the async_set_reset_local attribute to a process label using the following syntax.

attribute async_set_reset_local of process_label : label is ”signal_name_list”;

async_set_reset_local_all

Foundation Express treats all signals in the specified processes as if they have the async_set_reset attribute set to TRUE.

Attach the async_set_reset_local_all attribute to process labels by using the following syntax.

attribute async_set_reset_local_all of process_label_list : label is ”true”;

sync_set_reset

When this is set to TRUE on a signal, Foundation Express checks the signal to determine whether it synchronously sets or resets a register in the design.

Attach the sync_set_reset attribute to 1-bit signals by using the following syntax.

VHDL Reference Guide

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VHDL Reference Guide

attribute sync_set_reset of signal_name_list : signal is ”true”;

sync_set_reset_local

Foundation Express treats listed signals in the specified process as if they have the sync_set_reset attribute set to TRUE.

Attach the sync_set_reset_local attribute to a process label by using the following syntax.

attribute sync_set_reset_local of process_label : label is ”signal_name_list”;

sync_set_reset_local_all

Foundation Express treats all signals in the specified processes as if they have the sync_set_reset attribute set to TRUE.

Attach the sync_set_reset_local_all attribute to process labels by using the following syntax.

attribute sync_set_reset_local_all of process_label_list : label is ”true”;

one_cold

A one-cold implementation means that all signals in a group are active low and that only one signal can be active at a given time. The one_cold directive prevents Foundation Express from implementing priority encoding logic for the set and reset signals.

Add an assertion to the VHDL code to ensure that the group of signals has a one-cold implementation. Foundation Express does not produce any logic to check this assertion.

Attach the one_cold attribute to set or reset signals on sequential devices by using the following syntax.

attribute one_cold signal_name_list : signal is ”true”;

one_hot

A one_hot implementation means that all signals in a group are active-high and that only one signal can be active at a given time. The one_hot attribute prevents Foundation Express from implementing priority encoding logic for the set and reset signals.

Add an assertion to the VHDL code to ensure that the group of signals has a one_hot implementation. Foundation Express does not produce any logic to check this assertion.

Attach the one_hot attribute to set or reset signals on sequential devices using the following syntax.

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Xilinx Development System

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