VHDL Reference Guide

infix operators (they are used between operands). If you declared the overloaded operators without quotation marks, a VHDL tool considers them functions rather than operators.

Variable Declarations Variable declarations define a named value of a given type.

You can use variables in expressions, as described in the “Identifiers” section and “Literals” section of the “Expressions” chapter. You assign values to variables by using variable assignment statements, as described in the “Variable Assignment” section of the “Sequential Statements” chapter.

Foundation Express does not support variable initialization. If you try to initialize a variable, Foundation Express generates the following message.

Warning: Initial values for signals are not supported for synthesis. They are ignored on line %n (VHDL-2022)

The following example shows some variable declarations.

variable A, B: BIT; variable INIT: NEW_BIT;

Note: Variables are declared and used only in processes and subprograms, because processes and subprograms cannot declare signals for internal use.

To use these declarations in more than one entity or architecture, place them in a package, as described in the “Examples of Architectures for NAND2 Entity” section.

Type Declarations

You declare each signal with a type that determines the kind of data it carries. Types declared in an architecture are local to that architecture.

You can use type declarations in architectures, packages, entities, blocks, processes, and subprograms.

Type declarations define the name and characteristics of a type. Types and type declarations are fully described in the “Data Types” chapter. A type is a named set of values, such as the set of integers or the set (red, green, blue). An object of a given type, such as a signal, can have any value of that type.