Using Foundation Express with VHDL

circuits back to the VHDL description, perhaps to fine-tune architectural decisions.

•HDL descriptions supply technology-independent documentation of a design and its functionality.

An HDL description is more easily read and understood than a netlist or schematic description. Because the initial HDL design description is technology-independent, you can later reuse it to generate the design in a different technology, without having to translate from the original technology.

•VHDL, like most high-level software languages, provides strong type checking.

A component that expects a four-bit-wide signal type cannot be connected to a threeor five-bit-wide signal; this mismatch causes an error when the HDL description is compiled. If a variable’s range is defined as 1 to 15, an error results from assigning it a value of 0. Incorrectly using types is a major source of errors in descriptions. Type checking catches this kind of error in the HDL description even before a design is generated.

About VHDL

VHDL is one of a few HDLs in widespread use today. VHDL is recognized as a standard HDL by the Institute of Electrical and Electronics Engineers (IEEE Standard 1076, ratified in 1987) and by the United States Department of Defense (MIL-STD-454L).

VHDL divides entities (components, circuits, or systems) into an external or visible part (entity name and connections) and an internal or hidden part (entity algorithm and implementation). After you define the external interface to an entity, other entities can use that entity when they all are being developed. This concept of internal and external views is central to a VHDL view of system design. An entity is defined, relative to other entities, by its connections and behavior. You can explore alternate implementations (architectures) of an entity without changing the rest of the design.

After you define an entity for one design, you can reuse it in other designs as needed. You can develop libraries of entities to use with many designs or a family of designs.

A VHDL hardware model is shown in the following figure.

VHDL Reference Guide

Figure 1-1 VHDL Hardware Model

A VHDL entity (design) has one or more input, output, or inout ports that are connected (wired) to neighboring systems. An entity is composed of interconnected entities, processes, and components, all which operate concurrently. Each entity is defined by a particular architecture, which is composed of VHDL constructs such as arithmetic, signal assignment, or component instantiation statements.

In VHDL, independent processes model sequential (clocked) circuits, using flip-flops and latches, and combinatorial (unclocked) circuits, using only logic gates. Processes can define and call (instantiate) subprograms (subdesigns). Processes communicate with each other by signals (wires).

A signal has a source (driver), one or more destinations (receivers), and a user-defined type, such as “color” or “number between 0 and 15.”

Using Foundation Express with VHDL

VHDL provides a broad set of constructs. With VHDL, you can describe discrete electronic systems of varying complexity (systems, boards, chips, or modules) with varying levels of abstraction.

VHDL language constructs are divided into three categories by their level of abstraction: behavioral, dataflow, and structural. These categories are described as follows.

•Behavioral

The functional or algorithmic aspects of a design, expressed in a sequential VHDL process

•Dataflow

The view of data as flowing through a design, from input to output

An operation is defined in terms of a collection of data transformations, expressed as concurrent statements.

•Structural

The view closest to hardware; a model where the components of a design are interconnected

This view is expressed by component instantiations.

Foundation Express Design Process

Foundation Express performs three functions.

•Translates VHDL to an internal format

•Optimizes the block-level representation through various optimization methods

•Maps the design’s logical structure for a specific Xilinx technology library

Foundation Express synthesizes VHDL descriptions according to the VHDL synthesis policy defined in the “Design Descriptions” chapter. The Xilinx VHDL synthesis policy has three parts; design methodology, design style, and language constructs. You use the VHDL synthesis policy to produce high quality VHDL-based designs.

VHDL Reference Guide

Using Foundation Express to Compile a VHDL Design

When a VHDL design is read into Foundation Express, the design is converted to an internal database format so that Foundation Express can synthesize and optimize the design. Foundation Express restructures part or all of the design to optimize it. You control the degree of restructuring. Foundation Express includes the following restructuring options.

•Fully preserves a design’s hierarchy

•Moves full modules up or down in the hierarchy

•Combines certain modules with others

•Compresses the entire design into one module (called flattening the design)

The “Design Methodology” section describes the design process that uses Foundation Express with a VHDL simulator.

Design Methodology

The following figure shows a typical design process that uses Foundation Express and a VHDL simulator.

Using Foundation Express with VHDL

1

VHDL

Description

X8631

Figure 1-2 Design Flow

The numbers in the above figure are explained below.

1.Write a design description in VHDL.

This description can be a combination of structural and functional elements (as shown in the “Design Descriptions” chapter). Both Foundation Express and a VHDL simulator use this design description.

2.Provide VHDL test drivers for the simulator.

VHDL Reference Guide

The drivers supply test vectors for simulation and gather output data. To learn about writing these drivers, see the appropriate simulator manual.

3.Simulate the design by using a VHDL simulator and verify that the description is correct.

4.Using Foundation Express, synthesize and optimize the VHDL design descriptions into a gate-level netlist.

Foundation Express generates optimized netlists to satisfy timing constraints for a targeted FPGA architecture.

5.Using your Foundation development system, link the FPGA technology-specific version of the design to the VHDL simulator.

The development system includes simulation models and interfaces required for the design flow.

6.Simulate the technology-specific version of the design with the VHDL simulator.

You can use the original VHDL simulation drivers from Step 2, because module and port definitions are preserved through the translation and optimization processes.

7.Compare the output of the gate-level simulation (Step 6) against the output of the original VHDL description simulation (Step 3) to verify that the implementation is correct.