Chapter 5

Sequential Statements

Foundation Express interprets sequential statements, such as A:= 3, in the order in which they appear in code. VHDL sequential statements can appear only in processes and subprograms.

This chapter describes and illustrates the different types of sequential statements in the following sections.

•“Assignment Statements and Targets”

•“Variable Assignment Statements”

•“Signal Assignment Statements”

•“if Statements”

•“case Statements”

•“loop Statements”

•“next Statements”

•“exit Statements”

•“Subprograms”

•“return Statements”

•“wait Statements”

•“null Statements”

Assignment Statements and Targets

Use an assignment statement to assign a value to a variable or signal. The syntax follows.

target := expression; -- Variable assignment target <= expression; -- Signal assignment

VHDL Reference Guide

target is a variable or signal (or part of a variable or signal, such as a subarray) that receives the value of the expression. The expression must evaluate to the same type as the target. See the “Expressions” section of the “Expressions” chapter for more information.

There are five kinds of targets.

•Simple names, such as my_var

•Indexed names, such as my_array_var(3)

•Slices, such as my_array_var(3 to 6)

•Field names, such as my_record.a_field

•Aggregates, such as (my_var1, my_var2)

The difference in syntax between variable assignments and signal assignments follows.

•Variables use the := operator.

Variables are local to a process or subprogram, and their assignments take effect immediately.

•Signals use the <= operator.

Signals need to be global in a process or subprogram, and their assignments take effect at the end of a process. Signals are the only means of communication between processes. For more information on semantic differences, see the “Signal Assignment” section of this chapter.

Simple Name Targets

The syntax for an assignment to a simple name (identifier) target follows.

identifier := expression; -- Variable assignment identifier <= expression; -- Signal assignment

identifier is the name of a signal or variable. The assigned expression must have the same type as the signal or variable. For array types, all elements of the array are assigned values.

The following example shows assignments to simple name targets.

variable A, B: BIT;

Sequential Statements

C<= “1100"; -- Signal array C is assigned

--bit value “1100"

Indexed Name Targets

The syntax for an assignment to an indexed name (identifier) target follows.

variable A: BIT_VECTOR(1 to 4);

The example below shows two indexed name targets. One of the targets is computable, and the other is not. The figure following the example illustrates the corresponding design.

entity example5 3 is port (

signal A, B: BIT_VECTOR(0 to 3); signal I: INTEGER range 0 to 3; signal Y, Z: BIT;

);

end example5 3;

architecture behave of example5 3 is

VHDL Reference Guide

begin

process (I, Y, Z) begin

A<= “0000";

B<= “0000";

A(I) <= Y; -- Noncomputable index expression

B(3) <= Z; -- Computable index expression

Z B[3]

X8627

Figure 5-1 Design Illustrating Indexed Name Targets

Slice Targets

The syntax for an assignment to a slice target follows.

identifier(index_expr_1 direction index_expr_2)

identifier is the name of an array type signal or variable. Each index_expr expression must evaluate to an index value for the identifier array’s index type and bounds. Both index_expr expressions