VHDL Reference Guide

default. A default assignment is made to variables A and C in the example of fully specified variables.

Another way to ensure that you do not imply combinatorial feedback is to use a sequential process (one with a wait or if signal’event statement). In such a case, variables and signals are registered. The registers break the combinatorial feedback loop.

See the “Register and Three-State Inference” chapter for more information about sequential processes and the conditions under which Foundation Express infers registers and latches.

Asynchronous Behavior

Some forms of asynchronous behavior are not supported. An example is a circuit description of a one-hot signal generator of the following form.

X <= A nand (not(not(not A)));

You might expect this circuit description to generate three inverters (an inverting delay line) and a NAND gate, but it is optimized to the following.

X <= A nand (not A);

Then, it is optimized to the following.

X <= 1;

c[0] = a[0] & b[0];

for (i = 0; i <= 3; i = i + 1) c[i] = a[i] & b[i];

Understanding Superset Issues and Error Checking

The Foundation Express VHDL Analyzer is a full IEEE 1076 VHDL analyzer.

When Foundation Express reads in a VHDL design, it first calls the VHDL Analyzer to check the VHDL source for errors and then translates the VHDL source to an intermediate form for synthesis. If an error is in the VHDL source, you get a VHDL Analyzer message and possibly a VHDL Compiler message.

Writing Circuit Descriptions

VHDL Compiler allows globally static objects where only locally static objects are allowed, without issuing an error message.

VHDL Reference Guide