- •About This Manual
- •Additional Resources
- •Manual Contents
- •Conventions
- •Typographical
- •Online Document
- •Using Foundation Express with VHDL
- •Hardware Description Languages
- •Typical Uses for HDLs
- •Advantages of HDLs
- •About VHDL
- •Foundation Express Design Process
- •Using Foundation Express to Compile a VHDL Design
- •Design Methodology
- •Design Descriptions
- •Entities
- •Entity Generic Specifications
- •Entity Port Specifications
- •Architecture
- •Declarations
- •Components
- •Concurrent Statements
- •Constant Declarations
- •Processes
- •Signal Declarations
- •Subprograms
- •Type Declarations
- •Examples of Architectures for NAND2 Entity
- •Configurations
- •Packages
- •Using a Package
- •Package Structure
- •Package Declarations
- •Package Body
- •Resolution Functions
- •Data Types
- •Type Overview
- •Enumeration Types
- •Enumeration Overloading
- •Enumeration Encoding
- •Enumeration Encoding Values
- •Integer Types
- •Array Types
- •Constrained Array
- •Unconstrained Array
- •Array Attributes
- •Record Types
- •Record Aggregates
- •Predefined VHDL Data Types
- •Data Type BOOLEAN
- •Data Type BIT
- •Data Type CHARACTER
- •Data Type INTEGER
- •Data Type NATURAL
- •Data Type POSITIVE
- •Data Type STRING
- •Data Type BIT_VECTOR
- •Unsupported Data Types
- •Physical Types
- •Floating-Point Types
- •Access Types
- •File Types
- •Express Data Types
- •Subtypes
- •Expressions
- •Overview
- •Operators
- •Logical Operators
- •Relational Operators
- •Adding Operators
- •Unary (Signed) Operators
- •Multiplying Operators
- •Miscellaneous Arithmetic Operators
- •Operands
- •Operand Bit-Width
- •Computable Operands
- •Aggregates
- •Attributes
- •Expressions
- •Function Calls
- •Identifiers
- •Indexed Names
- •Literals
- •Numeric Literals
- •Character Literals
- •Enumeration Literals
- •String Literals
- •Qualified Expressions
- •Records and Fields
- •Slice Names
- •Limitations on Null Slices
- •Limitations on Noncomputable Slices
- •Type Conversions
- •Sequential Statements
- •Assignment Statements and Targets
- •Simple Name Targets
- •Indexed Name Targets
- •Slice Targets
- •Field Targets
- •Aggregate Targets
- •Variable Assignment Statements
- •Signal Assignment Statements
- •Variable Assignment
- •Signal Assignment
- •if Statements
- •Evaluating Conditions
- •Using the if Statement to Infer Registers and Latches
- •case Statements
- •Using Different Expression Types
- •Invalid case Statements
- •loop Statements
- •Basic loop Statement
- •while...loop Statements
- •for...loop Statements
- •Steps in the Execution of a for...loop Statement
- •for...loop Statements and Arrays
- •next Statements
- •exit Statements
- •Subprograms
- •Subprogram Always a Combinatorial Circuit
- •Subprogram Declaration and Body
- •Subprogram Calls
- •Procedure Calls
- •Function Calls
- •return Statements
- •Procedures and Functions as Design Components
- •Example with Component Implication Directives
- •Example without Component Implication Directives
- •wait Statements
- •Inferring Synchronous Logic
- •Combinatorial Versus Sequential Processes
- •null Statements
- •Concurrent Statements
- •Overview
- •process Statements
- •Combinatorial Process Example
- •Sequential Process Example
- •Driving Signals
- •block Statements
- •Nested Blocks
- •Guarded Blocks
- •Concurrent Versions of Sequential Statements
- •Concurrent Procedure Calls
- •Concurrent Signal Assignments
- •Simple Concurrent Signal Assignments
- •Conditional Signal Assignments
- •Selected Signal Assignments
- •Component Instantiation Statements
- •Direct Instantiation
- •generate Statements
- •for...generate Statements
- •Steps in the Execution of a for...generate Statement
- •Common Usage of a for...generate Statement
- •if...generate Statements
- •Register and Three-State Inference
- •Register Inference
- •The Inference Report
- •Latch Inference Warnings
- •Controlling Register Inference
- •Inferring Latches
- •Inferring Set/Reset (SR) Latches
- •Inferring D Latches
- •Inferring Master-Slave Latches
- •Inferring Flip-Flops
- •Inferring D Flip-Flops
- •Inferring JK Flip-Flops
- •Inferring Toggle Flip-Flops
- •Getting the Best Results
- •Understanding Limitations of Register Inference
- •Three-State Inference
- •Reporting Three-State Inference
- •Controlling Three-State Inference
- •Inferring Three-State Drivers
- •Inferring a Simple Three-State Driver
- •Three-State Driver with Registered Enable
- •Three-State Driver Without Registered Enable
- •Writing Circuit Descriptions
- •How Statements Are Mapped to Logic
- •Design Structure
- •Adding Structure
- •Using Variables and Signals
- •Using Parentheses
- •Using Design Knowledge
- •Optimizing Arithmetic Expressions
- •Arranging Expression Trees for Minimum Delay
- •Sharing Common Subexpressions
- •Changing an Operator Bit-Width
- •Using State Information
- •Propagating Constants
- •Sharing Complex Operators
- •Asynchronous Designs
- •Don’t Care Inference
- •Using Don’t Care Default Values
- •Differences Between Simulation and Synthesis
- •Synthesis Issues
- •Feedback Paths and Latches
- •Fully Specified Variables
- •Asynchronous Behavior
- •Understanding Superset Issues and Error Checking
- •Foundation Express Directives
- •Notation for Foundation Express Directives
- •Foundation Express Directives
- •Translation Stop and Start Pragma Directives
- •synthesis_off and synthesis_on Directives
- •Resolution Function Directives
- •Component Implication Directives
- •Foundation Express Packages
- •std_logic_1164 Package
- •std_logic_arith Package
- •Using the Package
- •Modifying the Package
- •Data Types
- •UNSIGNED
- •SIGNED
- •Conversion Functions
- •Arithmetic Functions
- •Example 10-1: Binary Arithmetic Functions
- •Example 10-2: Unary Arithmetic Functions
- •Comparison Functions
- •Example 10-3: Ordering Functions
- •Example 10-4: Equality Functions
- •Shift Functions
- •ENUM_ENCODING Attribute
- •pragma built_in
- •Type Conversion
- •numeric_std Package
- •Understanding the Limitations of numeric_std package
- •Using the Package
- •Data Types
- •Conversion Functions
- •Resize Function
- •Arithmetic Functions
- •Comparison Functions
- •Defining Logical Operators Functions
- •Shift Functions
- •Rotate Functions
- •Shift and Rotate Operators
- •std_logic_misc Package
- •ATTRIBUTES Package
- •VHDL Constructs
- •VHDL Construct Support
- •Design Units
- •Data Types
- •Declarations
- •Specifications
- •Names
- •Identifiers and Extended Identifiers
- •Specifics of Identifiers
- •Specifics of Extended Identifiers
- •Operators
- •Shift and Rotate Operators
- •xnor Operator
- •Operands and Expressions
- •Sequential Statements
- •Concurrent Statements
- •Predefined Language Environment
- •VHDL Reserved Words
- •Examples
- •Moore Machine
- •Mealy Machine
- •Read-Only Memory
- •Waveform Generator
- •Smart Waveform Generator
- •Definable-Width Adder-Subtracter
- •Count Zeros—Combinatorial Version
- •Count Zeros—Sequential Version
- •Soft Drink Machine—State Machine Version
- •Soft Drink Machine—Count Nickels Version
- •Carry-Lookahead Adder
- •Carry Value Computations
- •Implementation
- •Serial-to-Parallel Converter—Counting Bits
- •Input Format
- •Implementation Details
- •Serial-to-Parallel Converter—Shifting Bits
- •Programmable Logic Arrays
Register and Three-State Inference
Three-State Driver with Registered Enable
When a variable, such as THREE_STATE in the following example, is assigned to a register and defined as a three-state gate within the same process, Foundation Express also registers the enable pin of the three-state gate.
The following example shows this type of code, and the inference report for a three-state driver with registered enable follows the example. The figure “Three-State Driver with Registered Enable” shows the schematic the code generates, a three-state gate with a register on its enable pin.
library IEEE;
use IEEE.std_logic_1164.all;
entity three_state is
port ( DATA, CLK, THREE_STATE : in std_logic ; OUT1 : out std_logic );
end three_state;
architecture rtl of three_state is begin
infer : process (THREE_STATE, CLK) begin if (THREE_STATE = ’0’) then
OUT1 <= ’Z’;
elsif (CLK’event and CLK = ’1’) then OUT1 <= DATA;
end if;
end process infer;
end rtl;
The following example shows an inference report for a three-state driver with registered enable.
Register Name |
Type |
Widt |
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Bus |
MB |
AR |
AS |
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SR |
SS |
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ST |
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OUT1_reg |
Flip-flop |
1 |
- |
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N |
N |
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N |
N |
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N |
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Three-State Device Name |
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Type |
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OUT1_tri |
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Three-State Buffer |
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OUT1_tr_enable_reg |
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Flip-Flop (width 1) |
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OUT1_reg
set/reset/toggle: none
THREE_STATE 
CLK 
DATA |
OUT1 |
X8607
Figure 7-28 Three-State Driver with Registered Enable
Three-State Driver Without Registered Enable
The following example uses two processes to instantiate a three-state gate with a flip-flop on the input. The inference report for a threestate driver without registered enable follows the example. The figure “Three-State Driver without Registered Enable” shows the schematic the code generates.
library IEEE;
use IEEE.std_logic_1164.all;
entity ff_3state2 is
port ( DATA, CLK, THREE_STATE : in std_logic ; OUT1 : out std_logic );
end ff_3state2;
architecture rtl of ff_3state2 is signal TEMP : std_logic;
begin
process (CLK) begin
if (CLK’event and CLK = ’1’) then
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Register and Three-State Inference
TEMP <= DATA; end if;
end process;
process (THREE_STATE, TEMP) begin if (THREE_STATE = ’0’) then
OUT1 <= ’Z’; else
OUT1 <= TEMP; end if;
end process;
end rtl;
The following example shows an inference report for a three-state driver without registered enable.
Register Name |
Type |
Widt |
Bus |
MB |
AR |
AS |
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SR |
SS |
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ST |
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h |
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TEMP_reg |
Flip-flop |
1 |
- |
- |
N |
N |
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N |
N |
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N |
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Three-State Device Name |
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Type |
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MB |
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OUT1_tri |
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Three-State Buffer |
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N |
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TEMP_reg
set/reset/toggle: none
THREE_STATE 
DATA |
OUT1 |
CLK 

X8608
Figure 7-29 Three-State Driver without Registered Enable
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VHDL Reference Guide
Understanding the Limitations of Three-State
Inference
You can use the Z value in the following ways.
•Signal assignment
•Variable assignment
•Function call argument
•Return value
•Aggregate definition
You cannot use the Z value in an expression, except for comparison with Z. Be careful when using expressions that compare with the Z value. Foundation Express always evaluates these expressions to FALSE, and the preand post-synthesis simulation results might differ. For this reason, Foundation Express issues a warning when it synthesizes such comparisons.
The following example shows the incorrect use of the Z value in an expression.
OUT_VAL = (1’bz && IN_VAL);
The following example shows the correct use of the Z value in an expression.
if (IN_VAL == 1’bz) then
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