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Register and Three-State Inference

Three-State Driver with Registered Enable

When a variable, such as THREE_STATE in the following example, is assigned to a register and defined as a three-state gate within the same process, Foundation Express also registers the enable pin of the three-state gate.

The following example shows this type of code, and the inference report for a three-state driver with registered enable follows the example. The figure “Three-State Driver with Registered Enable” shows the schematic the code generates, a three-state gate with a register on its enable pin.

library IEEE;

use IEEE.std_logic_1164.all;

entity three_state is

port ( DATA, CLK, THREE_STATE : in std_logic ; OUT1 : out std_logic );

end three_state;

architecture rtl of three_state is begin

infer : process (THREE_STATE, CLK) begin if (THREE_STATE = ’0’) then

OUT1 <= ’Z’;

elsif (CLK’event and CLK = ’1’) then OUT1 <= DATA;

end if;

end process infer;

end rtl;

The following example shows an inference report for a three-state driver with registered enable.

Register Name

Type

Widt

 

Bus

MB

AR

AS

 

SR

SS

 

ST

 

 

 

h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUT1_reg

Flip-flop

1

-

-

N

N

 

N

N

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Three-State Device Name

 

 

Type

 

 

 

 

 

MB

 

 

 

 

 

 

 

 

 

 

OUT1_tri

 

 

 

Three-State Buffer

 

 

N

 

OUT1_tr_enable_reg

 

 

Flip-Flop (width 1)

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VHDL Reference Guide

7-51

VHDL Reference Guide

OUT1_reg

set/reset/toggle: none

THREE_STATE

CLK

DATA

OUT1

X8607

Figure 7-28 Three-State Driver with Registered Enable

Three-State Driver Without Registered Enable

The following example uses two processes to instantiate a three-state gate with a flip-flop on the input. The inference report for a threestate driver without registered enable follows the example. The figure “Three-State Driver without Registered Enable” shows the schematic the code generates.

library IEEE;

use IEEE.std_logic_1164.all;

entity ff_3state2 is

port ( DATA, CLK, THREE_STATE : in std_logic ; OUT1 : out std_logic );

end ff_3state2;

architecture rtl of ff_3state2 is signal TEMP : std_logic;

begin

process (CLK) begin

if (CLK’event and CLK = ’1’) then

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Xilinx Development System

Register and Three-State Inference

TEMP <= DATA; end if;

end process;

process (THREE_STATE, TEMP) begin if (THREE_STATE = ’0’) then

OUT1 <= ’Z’; else

OUT1 <= TEMP; end if;

end process;

end rtl;

The following example shows an inference report for a three-state driver without registered enable.

Register Name

Type

Widt

Bus

MB

AR

AS

 

SR

SS

 

ST

 

 

 

h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEMP_reg

Flip-flop

1

-

-

N

N

 

N

N

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Three-State Device Name

 

 

Type

 

 

 

 

 

MB

 

 

 

 

 

 

 

 

 

 

OUT1_tri

 

 

 

Three-State Buffer

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEMP_reg

set/reset/toggle: none

THREE_STATE

DATA

OUT1

CLK

X8608

Figure 7-29 Three-State Driver without Registered Enable

VHDL Reference Guide

7-53

VHDL Reference Guide

Understanding the Limitations of Three-State

Inference

You can use the Z value in the following ways.

Signal assignment

Variable assignment

Function call argument

Return value

Aggregate definition

You cannot use the Z value in an expression, except for comparison with Z. Be careful when using expressions that compare with the Z value. Foundation Express always evaluates these expressions to FALSE, and the preand post-synthesis simulation results might differ. For this reason, Foundation Express issues a warning when it synthesizes such comparisons.

The following example shows the incorrect use of the Z value in an expression.

OUT_VAL = (1’bz && IN_VAL);

The following example shows the correct use of the Z value in an expression.

if (IN_VAL == 1’bz) then

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Xilinx Development System

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