VHDL Reference Guide

•An adder that has A and 10 as inputs

•A multiplexer (implied by the if statement) that controls the final value of Y

if (B < 10)

Y = A + B; else

Y = A+ 10;

The logic blocks created by Foundation Express are custom-built for their environment. That is, if A and B are 4-bit quantities, a 4-bit adder is built. If A and B are 9-bit quantities, a 9-bit adder is built. Because Foundation Express incorporates a large set of these customized logic blocks, it can translate most VHDL statements and operators.

Design Structure

A design’s structure influences the size and complexity of the resulting synthesized circuit. These sections help you understand the following concepts.

•Adding Structure

•Using Design Knowledge

•Optimizing Arithmetic Expressions

•Changing an Operator Bit-Width

•Using State Information

•Propagating Constants

•Sharing Complex Operators

Adding Structure

Foundation Express gives you significant control over the preoptimization structure, or organization of components, in your design. Whether or not your design structure is preserved after optimization depends on the options you select.

Using Variables and Signals

You control design structure with your ordering of assignment statements and your use of variables. Each VHDL signal assignment,

Writing Circuit Descriptions

process, or component instantiation implies a piece of logic. Each variable or signal implies a wire. By using these constructs, you can connect entities in any configuration.

The following two examples show two possible descriptions of an adder’s carry chain. The figure following the examples illustrates the resulting design.

--A is the addend

--B is the augend

--C is the carry

--Cin is the carry in C0 <= (A0 and B0) or

((A0 or B0) and Cin); C1 <= (A1 and B1) or

((A1 or B1) and C0);

The following example shows a carry-lookahead chain.

--Ps are propagate

--Gs are generate p0 <= a0 or b0;

g0 <= a0 and b0;

p1 <= a1 or b1;

g1 <= a1 and b1;

c0 <= g0 or (p0 and cin);

c1 <= g1 or (p1 and g0) or

(p1 and p0 and cin);

Figure 8-1 Ripple Carry and Carry-Lookahead Chain Design

VHDL Reference Guide

Using Parentheses

Another way to control the structure of a design is to use parentheses to define logic groupings. The following example describes a 4-input adder grouping. The figure following the example illustrates the resulting design.

Z <= (A + B) + C + D;

Figure 8-2 Diagram of 4-Input Adder

The following example describes a 4-input adder grouping that is structured with parentheses. The figure following the example illustrates the design.

Z <= (A + B) + (C + D);