- •About This Manual
- •Additional Resources
- •Manual Contents
- •Conventions
- •Typographical
- •Online Document
- •Using Foundation Express with VHDL
- •Hardware Description Languages
- •Typical Uses for HDLs
- •Advantages of HDLs
- •About VHDL
- •Foundation Express Design Process
- •Using Foundation Express to Compile a VHDL Design
- •Design Methodology
- •Design Descriptions
- •Entities
- •Entity Generic Specifications
- •Entity Port Specifications
- •Architecture
- •Declarations
- •Components
- •Concurrent Statements
- •Constant Declarations
- •Processes
- •Signal Declarations
- •Subprograms
- •Type Declarations
- •Examples of Architectures for NAND2 Entity
- •Configurations
- •Packages
- •Using a Package
- •Package Structure
- •Package Declarations
- •Package Body
- •Resolution Functions
- •Data Types
- •Type Overview
- •Enumeration Types
- •Enumeration Overloading
- •Enumeration Encoding
- •Enumeration Encoding Values
- •Integer Types
- •Array Types
- •Constrained Array
- •Unconstrained Array
- •Array Attributes
- •Record Types
- •Record Aggregates
- •Predefined VHDL Data Types
- •Data Type BOOLEAN
- •Data Type BIT
- •Data Type CHARACTER
- •Data Type INTEGER
- •Data Type NATURAL
- •Data Type POSITIVE
- •Data Type STRING
- •Data Type BIT_VECTOR
- •Unsupported Data Types
- •Physical Types
- •Floating-Point Types
- •Access Types
- •File Types
- •Express Data Types
- •Subtypes
- •Expressions
- •Overview
- •Operators
- •Logical Operators
- •Relational Operators
- •Adding Operators
- •Unary (Signed) Operators
- •Multiplying Operators
- •Miscellaneous Arithmetic Operators
- •Operands
- •Operand Bit-Width
- •Computable Operands
- •Aggregates
- •Attributes
- •Expressions
- •Function Calls
- •Identifiers
- •Indexed Names
- •Literals
- •Numeric Literals
- •Character Literals
- •Enumeration Literals
- •String Literals
- •Qualified Expressions
- •Records and Fields
- •Slice Names
- •Limitations on Null Slices
- •Limitations on Noncomputable Slices
- •Type Conversions
- •Sequential Statements
- •Assignment Statements and Targets
- •Simple Name Targets
- •Indexed Name Targets
- •Slice Targets
- •Field Targets
- •Aggregate Targets
- •Variable Assignment Statements
- •Signal Assignment Statements
- •Variable Assignment
- •Signal Assignment
- •if Statements
- •Evaluating Conditions
- •Using the if Statement to Infer Registers and Latches
- •case Statements
- •Using Different Expression Types
- •Invalid case Statements
- •loop Statements
- •Basic loop Statement
- •while...loop Statements
- •for...loop Statements
- •Steps in the Execution of a for...loop Statement
- •for...loop Statements and Arrays
- •next Statements
- •exit Statements
- •Subprograms
- •Subprogram Always a Combinatorial Circuit
- •Subprogram Declaration and Body
- •Subprogram Calls
- •Procedure Calls
- •Function Calls
- •return Statements
- •Procedures and Functions as Design Components
- •Example with Component Implication Directives
- •Example without Component Implication Directives
- •wait Statements
- •Inferring Synchronous Logic
- •Combinatorial Versus Sequential Processes
- •null Statements
- •Concurrent Statements
- •Overview
- •process Statements
- •Combinatorial Process Example
- •Sequential Process Example
- •Driving Signals
- •block Statements
- •Nested Blocks
- •Guarded Blocks
- •Concurrent Versions of Sequential Statements
- •Concurrent Procedure Calls
- •Concurrent Signal Assignments
- •Simple Concurrent Signal Assignments
- •Conditional Signal Assignments
- •Selected Signal Assignments
- •Component Instantiation Statements
- •Direct Instantiation
- •generate Statements
- •for...generate Statements
- •Steps in the Execution of a for...generate Statement
- •Common Usage of a for...generate Statement
- •if...generate Statements
- •Register and Three-State Inference
- •Register Inference
- •The Inference Report
- •Latch Inference Warnings
- •Controlling Register Inference
- •Inferring Latches
- •Inferring Set/Reset (SR) Latches
- •Inferring D Latches
- •Inferring Master-Slave Latches
- •Inferring Flip-Flops
- •Inferring D Flip-Flops
- •Inferring JK Flip-Flops
- •Inferring Toggle Flip-Flops
- •Getting the Best Results
- •Understanding Limitations of Register Inference
- •Three-State Inference
- •Reporting Three-State Inference
- •Controlling Three-State Inference
- •Inferring Three-State Drivers
- •Inferring a Simple Three-State Driver
- •Three-State Driver with Registered Enable
- •Three-State Driver Without Registered Enable
- •Writing Circuit Descriptions
- •How Statements Are Mapped to Logic
- •Design Structure
- •Adding Structure
- •Using Variables and Signals
- •Using Parentheses
- •Using Design Knowledge
- •Optimizing Arithmetic Expressions
- •Arranging Expression Trees for Minimum Delay
- •Sharing Common Subexpressions
- •Changing an Operator Bit-Width
- •Using State Information
- •Propagating Constants
- •Sharing Complex Operators
- •Asynchronous Designs
- •Don’t Care Inference
- •Using Don’t Care Default Values
- •Differences Between Simulation and Synthesis
- •Synthesis Issues
- •Feedback Paths and Latches
- •Fully Specified Variables
- •Asynchronous Behavior
- •Understanding Superset Issues and Error Checking
- •Foundation Express Directives
- •Notation for Foundation Express Directives
- •Foundation Express Directives
- •Translation Stop and Start Pragma Directives
- •synthesis_off and synthesis_on Directives
- •Resolution Function Directives
- •Component Implication Directives
- •Foundation Express Packages
- •std_logic_1164 Package
- •std_logic_arith Package
- •Using the Package
- •Modifying the Package
- •Data Types
- •UNSIGNED
- •SIGNED
- •Conversion Functions
- •Arithmetic Functions
- •Example 10-1: Binary Arithmetic Functions
- •Example 10-2: Unary Arithmetic Functions
- •Comparison Functions
- •Example 10-3: Ordering Functions
- •Example 10-4: Equality Functions
- •Shift Functions
- •ENUM_ENCODING Attribute
- •pragma built_in
- •Type Conversion
- •numeric_std Package
- •Understanding the Limitations of numeric_std package
- •Using the Package
- •Data Types
- •Conversion Functions
- •Resize Function
- •Arithmetic Functions
- •Comparison Functions
- •Defining Logical Operators Functions
- •Shift Functions
- •Rotate Functions
- •Shift and Rotate Operators
- •std_logic_misc Package
- •ATTRIBUTES Package
- •VHDL Constructs
- •VHDL Construct Support
- •Design Units
- •Data Types
- •Declarations
- •Specifications
- •Names
- •Identifiers and Extended Identifiers
- •Specifics of Identifiers
- •Specifics of Extended Identifiers
- •Operators
- •Shift and Rotate Operators
- •xnor Operator
- •Operands and Expressions
- •Sequential Statements
- •Concurrent Statements
- •Predefined Language Environment
- •VHDL Reserved Words
- •Examples
- •Moore Machine
- •Mealy Machine
- •Read-Only Memory
- •Waveform Generator
- •Smart Waveform Generator
- •Definable-Width Adder-Subtracter
- •Count Zeros—Combinatorial Version
- •Count Zeros—Sequential Version
- •Soft Drink Machine—State Machine Version
- •Soft Drink Machine—Count Nickels Version
- •Carry-Lookahead Adder
- •Carry Value Computations
- •Implementation
- •Serial-to-Parallel Converter—Counting Bits
- •Input Format
- •Implementation Details
- •Serial-to-Parallel Converter—Shifting Bits
- •Programmable Logic Arrays
VHDL Reference Guide
sequential_statement; else
sequential_statement; end if;
•An edge expression cannot be part of another logical expression or be used as an argument.
The following function call is invalid, because you cannot use the edge expression as an argument.
any_function(edge);
Three-State Inference
Foundation Express infers a three-state driver when you assign the value of Z to a variable. The Z value represents the high-impedance state. Foundation Express infers one three-state driver per process.
You can assign high-impedance values to single-bit or bused signals (or variables).
Reporting Three-State Inference
The following example shows a three-state inference report.
Three-State Device Name |
Type |
MB |
|
|
|
OUT1_tri |
Three-State Buffer |
N |
|
|
|
The first column of the report indicates the name of the inferred three-state device. The second column of the report indicates the type of three-state device that Foundation Express inferred. The third column indicates whether the three-state device has multiple bits.
Controlling Three-State Inference
Foundation Express always infers a three-state driver when you assign the value of Z to a signal or variable. Foundation Express does not provide any means of controlling the inference.
Inferring Three-State Drivers
This section contains VHDL examples that infer the following types of three-state drivers.
•Simple three-state driver
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Register and Three-State Inference
•Three-state driver with registered enable
•Three-state driver without registered enable
Inferring a Simple Three-State Driver
This section provides a template for a simple three-state driver. In addition, this section supplies examples of how allocating highimpedance assignments to different processes affects three-state inference.
The following example provides the VHDL template for a simple three-state driver. Foundation Express generates the inference report shown following the example for a simple three-state driver. The figure “Three-State Driver” shows the inferred three-state driver.
library IEEE, synopsys;
use IEEE.std_logic_1164.all; entity three_state is
port(IN1, ENABLE : in std_logic; OUT1 : out std_logic );
end;
architecture rtl of three_state is begin
process (IN1, ENABLE) begin if (ENABLE = ’1’) then
OUT1 <= IN1; else
OUT1 <= ’Z’; -- assigns high-impedance state end if;
end process;
end rtl;
The following example shows an inference report for a simple threestate driver.
Three-State Device Name |
Type |
MB |
|
|
|
OUT1_tri |
Three-State Buffer |
N |
|
|
|
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ENABLE 
IN1 

OUT
X8604
Figure 7-25 Simple Three-State Driver
Inferring One Three-State Driver from a Single Process The following example shows how to place all high-impedance assignments in a single process. In this case, the data is gated and Foundation Express infers a single three-state driver. An inference report for a single process follows the example. The figure “Inferring One Three-State Driver” shows the schematic the code generates.
library IEEE;
use IEEE.std_logic_1164.all;
entity three_state is
port ( A, B, SELA, SELB : in std_logic ; T : out std_logic );
end three_state;
architecture rtl of three_state is begin
infer : process (SELA, A, SELB, B) begin T <= ’Z’;
if (SELA = ’1’) then T <= A;
elsif (SELB = ’1’) then T <= B;
end if;
end process infer;
end rtl;
The following example shows a single block inference report.
Three-State Device Name |
Type |
MB |
|
|
|
T_tri |
Three-State Buffer |
N |
|
|
|
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Register and Three-State Inference
Figure 7-26 Inferring One Three-State Driver
Inferring Three-State Drivers from Separate Processes The following example shows how to place each high-impedance assignment in a separate process. In this case, Foundation Express infers multiple three-state drivers.
The inference report for two three-state drivers follows the example.
The figure “Inferring Two Three-State Drivers” shows the schematic the code generates.
library IEEE;
use IEEE.std_logic_1164.all;
entity three_state is
port ( A, B, SELA, SELB : in std_logic ; T : out std_logic );
end three_state;
architecture rtl of three_state is begin
infer1 : process (SELA, A) begin if (SELA = ’1’) then
T <= A;
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else
T <= ’Z’; end if;
end process infer1;
infer2 : process (SELB, B) begin if (SELB = ’1’) then
T <= B; else
T <= ’Z’; end if;
end process infer2;
end rtl;
The following example shows an inference report for two three-state drivers from separate processes.
Three-State Device Name |
Type |
MB |
|
|
|
T_tri |
Three-State Buffer |
N |
|
|
|
|
|
|
Three-State Device Name |
Type |
MB |
|
|
|
T_tri2 |
Three-State Buffer |
N |
|
|
|
SELA 
A 


T
SELB 
B 
X8606
Figure 7-27 Inferring Two Three-State Drivers
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