VHDL Reference Guide

end block; end RTL;

A concurrent assignment within a block statement can use the guarded keyword. In such a case, the guard expression conditions the signal assignment. The description in the following example produces a level-sensitive latch.

entity EG2 is

port (d, g: in BIT; q: out BIT); end;

architecture RTL of EG2 is begin

guarded_block: block (g = ’1’) begin

q <= guarded d; end block;

end RTL;

Note: Do not use the ’event or ’stable attributes with the guard expression if you want to produce an edge-triggered latch using a guarded block. The presence of either attribute prevents it.

Concurrent Versions of Sequential Statements

This section describes concurrent versions of sequential statements in the following form.

•Concurrent Procedure Calls

•Concurrent Signal Assignments

•Simple Concurrent Signal Assignments

•Conditional Signal Assignments

•Selected Signal Assignments

Concurrent Procedure Calls

A concurrent procedure call, which is used in an architecture construct or a block statement, is equivalent to a process with a single sequential procedure call in it (see the following example). The syntax is the same as that of a sequential procedure call.

procedure_name [ ( [ name => ] expression

{ , [ name => ] expression } ) ] ;

Concurrent Statements

The equivalent process reads all the in and inout parameters of the procedure. The following example shows a procedure declaration and a concurrent procedure call and its equivalent process.

procedure ADD(signal A, B: in BIT; signal SUM: out BIT);

Foundation Express implements procedure and function calls with logic unless you use the map_to_entity compiler directive. (See the

“Procedures and Functions as Design Components” section of the “Sequential Statements” chapter.)

A common use for concurrent procedure calls is to obtain many copies of a procedure. For example, assume that a class of BIT_VECTOR signals must have just 1 bit with value ’1’ and the rest of the bits with value ‘0’ (as in the following example). Suppose you have several signals of varying widths that you want monitored at the same time (as the second example following). One approach is to write a procedure to detect the error in a BIT_VECTOR signal, and then make a concurrent call to that procedure for each signal.

The following example shows a procedure, CHECK, that determines whether a given bit vector has exactly one element with value ’1.’ If this is not the case, CHECK sets its out parameter ERROR to TRUE, as the example shows.

VHDL Reference Guide

FOUND_ONE := TRUE; end if;

end loop;

ERROR <= not FOUND_ONE; -- Error will be TRUE if -- no ’1’ seen

end;

The following example shows the CHECK procedure called concurrently for four differently sized bit vector signals. The resulting circuit design is shown in the figure following the example.

BLK: block

signal S1: BIT_VECTOR(0 to 0); signal S2: BIT_VECTOR(0 to 1); signal S3: BIT_VECTOR(0 to 2); signal S4: BIT_VECTOR(0 to 3);

signal E1, E2, E3, E4: BOOLEAN;

begin

CHECK(S1, E1); -- Concurrent procedure call CHECK(S2, E2);

CHECK(S3, E3);

CHECK(S4, E4); end block BLK;

Figure 6-5 Concurrent CHECK Procedure Design