Design Descriptions
•out can only be assigned a value.
•inout can be read and assigned a value. The value read is that of the port’s incoming value, not the assigned value (if any).
•buffer is similar to out but can be read. The value read is the assigned value. It can have only one driver. For more information about drivers, see “Driving Signals.”
•port_type is a previously defined data type.
The following example shows an entity specification for a 2-input N- bit comparator with a default bit-width of 8.
--Define an entity (design) called COMP
--that has 2 N-bit inputs and one output.
entity COMP is |
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generic(N: INTEGER := 8); |
-- default is 8 bits |
port(X, Y: in BIT_VECTOR(0 to N-1); EQUAL: out BOOLEAN);
end COMP;
Architecture
Architecture, which determines the implementation of an entity, can range in abstraction from an algorithm (a set of sequential statements within a process) to a structural netlist (a set of component instantiations).
The syntax follows.
architecture architecture_name of entity_name is
{block_declarative_item } begin
{concurrent_statement } end [ architecture_name ] ;
•architecture_name is the name of the architecture.
•entity_name is the name of the entity being implemented.
•block_declarative_item is any of the following statements.
•use statement (See the “Type Declarations” section of this chapter.)
•Subprogram Declarations
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VHDL Reference Guide
•Subprogram Body
•Type Declarations
•Subtype Declarations
•Constant Declarations
•Signal Declarations
•Concurrent Statements
Define a unit of computation that reads signals, performs computations, and assigns values to signals
The following example shows a description for a 3-bit counter that contains an entity specification and an architecture statement.
•Entity specification for COUNTER3
•Architecture statement, MY_ARCH
entity COUNTER3 is port ( CLK : in bit;
RESET: in bit;
COUNT: out integer range 0 to 7); end COUNTER3;
architecture MY_ARCH of COUNTER3 is signal COUNT_tmp : integer range 0 to 7;
begin process begin
wait until (CLK’event and CLK = ’1’);
--wait for the clock
if RESET = ’1’ or COUNT_tmp = 7 then
-- Check for RESET or max. count COUNT_tmp <= 0;
else COUNT_tmp <= COUNT_tmp + 1; -- Keep counting
end if; end process;
COUNT <= COUNT_tmp; end MY_ARCH;
The following figure shows a schematic of the previous example.
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Design Descriptions
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COUNT |
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CLK |
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MUX21H |
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NR2 |
COUNT |
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FD1 |
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NR2 |
MUX21H |
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RESET |
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COUNT |
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NR2 |
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X8665 |
Figure 2-1 3-Bit Counter Synthesized Circuit
Note: In an architecture, you must not give constants or signals the same name as any of the entity’s ports in the entity specification.
If you declare a constant or signal with a port’s name, the new declaration hides that port name. If the new declaration lies directly in the architecture declaration (as shown in the following example) and not in an inner block, Foundation Express reports an error.
entity X is
port(SIG, CONST: in BIT; OUT1, OUT2: out BIT);
end X;
architecture EXAMPLE of X is signal SIG : BIT; constant CONST: BIT := ’1’;
begin
...
end EXAMPLE;
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