Chapter 4

Expressions

In VHDL, expressions perform arithmetic or logical computations by applying an operator to one or more operands. Operators specify the computation to be performed. Operands are the data for the computation.

The following sections of this chapter discuss the individual components and use of expressions in a design description.

•“Overview”

•“Operators”

•“Operands”

Overview

In the following VHDL fragment, A and B are operands, + is an operator, and A + B is an expression.

C := A + B; -- Computes the sum of two values

You can use expressions in many places in a design description.

Expressions can be used in any of the following ways.

•Assign them to variables or signals or use them as the initial values of constants

•Use them as operands to other operators

•Use them for the return value of functions

•Use them for the IN parameters in a subprogram call

•Assign them to the OUT parameters in a procedure body

•Use them to control the actions of statements such as if, loop, and case