VHDL Reference Guide

Only the following predefined attributes are supported; base, left, right, high, low, range, reverse_range, and length. The event and stable attributes are supported only as described with the wait and if statements. (See the “wait Statements” section of the “Sequential Statements” chapter.) User-defined attribute names are unsupported. The use of attributes with selected names (name.name’attribute) is unsupported.

Identifiers and Extended Identifiers

An identifier in VHDL is a user-defined name for any of the following: constant, variable, function, signal, entity, port, subprogram, parameter, and instance.

Specifics of Identifiers

The characteristics of identifiers follow.

•They can be composed of letters, digits, and the underscore character ( _ ).

•Their first character cannot be a number, unless it is an extended identifier (see the example in the next section).

•They can be of any length.

•They are case-insensitive.

•All of their characters are significant.

Specifics of Extended Identifiers

The characteristics of extended identifiers follow.

•Any of the following can be defined as an extended identifier.

•Identifiers that contain special characters

•Identifiers that begin with numbers

•Identifiers that have the same name as a keyword

•They start with a backslash character (\), followed by a sequence of characters, followed by another backslash (\).

•They are case-sensitive.

The following example shows some extended identifiers.