- •About This Manual
- •Additional Resources
- •Manual Contents
- •Conventions
- •Typographical
- •Online Document
- •Using Foundation Express with VHDL
- •Hardware Description Languages
- •Typical Uses for HDLs
- •Advantages of HDLs
- •About VHDL
- •Foundation Express Design Process
- •Using Foundation Express to Compile a VHDL Design
- •Design Methodology
- •Design Descriptions
- •Entities
- •Entity Generic Specifications
- •Entity Port Specifications
- •Architecture
- •Declarations
- •Components
- •Concurrent Statements
- •Constant Declarations
- •Processes
- •Signal Declarations
- •Subprograms
- •Type Declarations
- •Examples of Architectures for NAND2 Entity
- •Configurations
- •Packages
- •Using a Package
- •Package Structure
- •Package Declarations
- •Package Body
- •Resolution Functions
- •Data Types
- •Type Overview
- •Enumeration Types
- •Enumeration Overloading
- •Enumeration Encoding
- •Enumeration Encoding Values
- •Integer Types
- •Array Types
- •Constrained Array
- •Unconstrained Array
- •Array Attributes
- •Record Types
- •Record Aggregates
- •Predefined VHDL Data Types
- •Data Type BOOLEAN
- •Data Type BIT
- •Data Type CHARACTER
- •Data Type INTEGER
- •Data Type NATURAL
- •Data Type POSITIVE
- •Data Type STRING
- •Data Type BIT_VECTOR
- •Unsupported Data Types
- •Physical Types
- •Floating-Point Types
- •Access Types
- •File Types
- •Express Data Types
- •Subtypes
- •Expressions
- •Overview
- •Operators
- •Logical Operators
- •Relational Operators
- •Adding Operators
- •Unary (Signed) Operators
- •Multiplying Operators
- •Miscellaneous Arithmetic Operators
- •Operands
- •Operand Bit-Width
- •Computable Operands
- •Aggregates
- •Attributes
- •Expressions
- •Function Calls
- •Identifiers
- •Indexed Names
- •Literals
- •Numeric Literals
- •Character Literals
- •Enumeration Literals
- •String Literals
- •Qualified Expressions
- •Records and Fields
- •Slice Names
- •Limitations on Null Slices
- •Limitations on Noncomputable Slices
- •Type Conversions
- •Sequential Statements
- •Assignment Statements and Targets
- •Simple Name Targets
- •Indexed Name Targets
- •Slice Targets
- •Field Targets
- •Aggregate Targets
- •Variable Assignment Statements
- •Signal Assignment Statements
- •Variable Assignment
- •Signal Assignment
- •if Statements
- •Evaluating Conditions
- •Using the if Statement to Infer Registers and Latches
- •case Statements
- •Using Different Expression Types
- •Invalid case Statements
- •loop Statements
- •Basic loop Statement
- •while...loop Statements
- •for...loop Statements
- •Steps in the Execution of a for...loop Statement
- •for...loop Statements and Arrays
- •next Statements
- •exit Statements
- •Subprograms
- •Subprogram Always a Combinatorial Circuit
- •Subprogram Declaration and Body
- •Subprogram Calls
- •Procedure Calls
- •Function Calls
- •return Statements
- •Procedures and Functions as Design Components
- •Example with Component Implication Directives
- •Example without Component Implication Directives
- •wait Statements
- •Inferring Synchronous Logic
- •Combinatorial Versus Sequential Processes
- •null Statements
- •Concurrent Statements
- •Overview
- •process Statements
- •Combinatorial Process Example
- •Sequential Process Example
- •Driving Signals
- •block Statements
- •Nested Blocks
- •Guarded Blocks
- •Concurrent Versions of Sequential Statements
- •Concurrent Procedure Calls
- •Concurrent Signal Assignments
- •Simple Concurrent Signal Assignments
- •Conditional Signal Assignments
- •Selected Signal Assignments
- •Component Instantiation Statements
- •Direct Instantiation
- •generate Statements
- •for...generate Statements
- •Steps in the Execution of a for...generate Statement
- •Common Usage of a for...generate Statement
- •if...generate Statements
- •Register and Three-State Inference
- •Register Inference
- •The Inference Report
- •Latch Inference Warnings
- •Controlling Register Inference
- •Inferring Latches
- •Inferring Set/Reset (SR) Latches
- •Inferring D Latches
- •Inferring Master-Slave Latches
- •Inferring Flip-Flops
- •Inferring D Flip-Flops
- •Inferring JK Flip-Flops
- •Inferring Toggle Flip-Flops
- •Getting the Best Results
- •Understanding Limitations of Register Inference
- •Three-State Inference
- •Reporting Three-State Inference
- •Controlling Three-State Inference
- •Inferring Three-State Drivers
- •Inferring a Simple Three-State Driver
- •Three-State Driver with Registered Enable
- •Three-State Driver Without Registered Enable
- •Writing Circuit Descriptions
- •How Statements Are Mapped to Logic
- •Design Structure
- •Adding Structure
- •Using Variables and Signals
- •Using Parentheses
- •Using Design Knowledge
- •Optimizing Arithmetic Expressions
- •Arranging Expression Trees for Minimum Delay
- •Sharing Common Subexpressions
- •Changing an Operator Bit-Width
- •Using State Information
- •Propagating Constants
- •Sharing Complex Operators
- •Asynchronous Designs
- •Don’t Care Inference
- •Using Don’t Care Default Values
- •Differences Between Simulation and Synthesis
- •Synthesis Issues
- •Feedback Paths and Latches
- •Fully Specified Variables
- •Asynchronous Behavior
- •Understanding Superset Issues and Error Checking
- •Foundation Express Directives
- •Notation for Foundation Express Directives
- •Foundation Express Directives
- •Translation Stop and Start Pragma Directives
- •synthesis_off and synthesis_on Directives
- •Resolution Function Directives
- •Component Implication Directives
- •Foundation Express Packages
- •std_logic_1164 Package
- •std_logic_arith Package
- •Using the Package
- •Modifying the Package
- •Data Types
- •UNSIGNED
- •SIGNED
- •Conversion Functions
- •Arithmetic Functions
- •Example 10-1: Binary Arithmetic Functions
- •Example 10-2: Unary Arithmetic Functions
- •Comparison Functions
- •Example 10-3: Ordering Functions
- •Example 10-4: Equality Functions
- •Shift Functions
- •ENUM_ENCODING Attribute
- •pragma built_in
- •Type Conversion
- •numeric_std Package
- •Understanding the Limitations of numeric_std package
- •Using the Package
- •Data Types
- •Conversion Functions
- •Resize Function
- •Arithmetic Functions
- •Comparison Functions
- •Defining Logical Operators Functions
- •Shift Functions
- •Rotate Functions
- •Shift and Rotate Operators
- •std_logic_misc Package
- •ATTRIBUTES Package
- •VHDL Constructs
- •VHDL Construct Support
- •Design Units
- •Data Types
- •Declarations
- •Specifications
- •Names
- •Identifiers and Extended Identifiers
- •Specifics of Identifiers
- •Specifics of Extended Identifiers
- •Operators
- •Shift and Rotate Operators
- •xnor Operator
- •Operands and Expressions
- •Sequential Statements
- •Concurrent Statements
- •Predefined Language Environment
- •VHDL Reserved Words
- •Examples
- •Moore Machine
- •Mealy Machine
- •Read-Only Memory
- •Waveform Generator
- •Smart Waveform Generator
- •Definable-Width Adder-Subtracter
- •Count Zeros—Combinatorial Version
- •Count Zeros—Sequential Version
- •Soft Drink Machine—State Machine Version
- •Soft Drink Machine—Count Nickels Version
- •Carry-Lookahead Adder
- •Carry Value Computations
- •Implementation
- •Serial-to-Parallel Converter—Counting Bits
- •Input Format
- •Implementation Details
- •Serial-to-Parallel Converter—Shifting Bits
- •Programmable Logic Arrays
VHDL Reference Guide
signal S4: SIGNED (3 downto 0); signal S8: SIGNED (7 downto 0);
Table 10-2 Number of Bits Returned by + and -
+ or - |
U4 |
U8 |
S4 |
S8 |
|
|
|
|
|
U4 |
4 |
8 |
5 |
8 |
U8 |
8 |
8 |
9 |
9 |
S4 |
5 |
9 |
4 |
8 |
S8 |
8 |
9 |
8 |
8 |
In some circumstances, you might need to obtain a carry-out bit from the + or - operation. To do this, extend the larger operand by one bit. The high bit of the return value is the carry-out bit, as illustrated in the example below.
process
variable a, b, sum: UNSIGNED (7 downto 0); variable temp: UNSIGNED (8 downto 0); variable carry: BIT;
begin
temp := CONV_UNSIGNED(a,9) + b; sum := temp(7 downto 0);
carry := temp(8); end process;
Comparison Functions
The std_logic_arith package provides functions to compare UNSIGNED and SIGNED data types with each other and with the predefined type INTEGER. Foundation Express compares the numeric values of the arguments, returning a BOOLEAN value. For example, the following expression evaluates TRUE.
UNSIGNED’("001") > SIGNED’("111")
The std_logic_arith comparison functions are similar to the built-in VHDL comparison functions. The only difference is that the std_logic_arith functions accommodate signed numbers and varying bit-widths. The predefined VHDL comparison functions perform bit-wise comparisons and so do not have the correct semantics for comparing numeric values. (See the “Relational Operators” section of the “Expressions” chapter.)
10-10 |
Xilinx Development System |
Foundation Express Packages
These functions produce comparators. The function declarations are listed in two groups, ordering functions (<, <=, >, and >=) and equality functions (= and /=) in the following examples.
Example 10-3: Ordering Functions
function "<"(L: UNSIGNED; |
R: UNSIGNED) return Boolean; |
|
function "<"(L: SIGNED; |
R: SIGNED) |
return Boolean; |
function "<"(L: UNSIGNED; |
R: SIGNED) |
return Boolean; |
function "<"(L: SIGNED; |
R: UNSIGNED) return Boolean; |
|
function "<"(L: UNSIGNED; |
R: INTEGER) |
return Boolean; |
function "<"(L: INTEGER; |
R: UNSIGNED) return Boolean; |
|
function "<"(L: SIGNED; |
R: INTEGER) |
return Boolean; |
function "<"(L: INTEGER; |
R: SIGNED) |
return Boolean; |
function "<="(L: UNSIGNED; |
R: UNSIGNED) |
return Boolean; |
function "<="(L: SIGNED; |
R: SIGNED) |
return Boolean; |
function "<="(L: UNSIGNED; |
R: SIGNED) |
return Boolean; |
function "<="(L: SIGNED; |
R: UNSIGNED) |
return Boolean; |
function "<="(L: UNSIGNED; |
R: INTEGER) |
return Boolean; |
function "<="(L: INTEGER; |
R: UNSIGNED) |
return Boolean; |
function "<="(L: SIGNED; |
R: INTEGER) |
return Boolean; |
function "<="(L: INTEGER; |
R: SIGNED) |
return Boolean; |
function "" functions">">"(L: UNSIGNED; R: UNSIGNED) return Boolean;
function ">"(L: SIGNED; |
R: SIGNED) |
return Boolean; |
function ">"(L: UNSIGNED; |
R: SIGNED) |
return Boolean; |
function ">"(L: SIGNED; |
R: UNSIGNED) return Boolean; |
|
function ">"(L: UNSIGNED; |
R: INTEGER) |
return Boolean; |
function ">"(L: INTEGER; |
R: UNSIGNED) return Boolean; |
|
function ">"(L: SIGNED; |
R: INTEGER) |
return Boolean; |
function ">"(L: INTEGER; |
R: SIGNED) |
return Boolean; |
function ="" functions">">="(L: UNSIGNED; R: UNSIGNED) return Boolean;
function ">="(L: SIGNED; |
R: SIGNED) |
return Boolean; |
function ">="(L: UNSIGNED; |
R: SIGNED) |
return Boolean; |
function ">="(L: SIGNED; |
R: UNSIGNED) |
return Boolean; |
function ">="(L: UNSIGNED; |
R: INTEGER) |
return Boolean; |
function ">="(L: INTEGER; |
R: UNSIGNED) |
return Boolean; |
function ">="(L: SIGNED; |
R: INTEGER) |
return Boolean; |
function ">="(L: INTEGER; |
R: SIGNED) |
return Boolean; |
Example 10-4: Equality Functions
function "="(L: UNSIGNED; |
R: UNSIGNED) return Boolean; |
|||
function |
"="(L: SIGNED; |
R: SIGNED) |
return |
Boolean; |
function |
"="(L: UNSIGNED; |
R: SIGNED) |
return |
Boolean; |
VHDL Reference Guide |
10-11 |
