Writing Circuit Descriptions

Y <= A + B + C;

Z <= D + A + B;

The parser does not recognize A + B as a common subexpression, because it parses the second equation as (D + A) + B. You can force the parser to recognize the common subexpression by rewriting the second assignment statement as follows.

Z <= A + B + D;

or

Z <= D + (A + B);

Note: You do not have to rewrite the assignment statement, because Foundation Express recognizes common subexpressions automatically.

Changing an Operator Bit-Width

The adder in the following example sums the 8-bit value of A (a

BYTE) with the 8-bit value of TEMP. TEMP’s value is either B, which is used only when it is less than 16, or C, which is a 4-bit value (a NIBBLE).Therefore, the upper four bits of TEMP are always 0. Foundation Express cannot derive this fact, because TEMP is declared with type BYTE.

You can simplify the synthesized circuit by changing the declared type of TEMP to NIBBLE (a 4-bit value). With this modification, half adders, rather than full adders, are required to implement the top four bits of the adder circuit, which figure, “Function with One Adder Schematic,” illustrates.

function ADD_IT_16 (A, B: BYTE; C: NIBBLE) return BYTE is variable TEMP: BYTE;

begin

if B < 16 then TEMP <= B;

else

TEMP <= C; end if;

return A + TEMP; end;

VHDL Reference Guide

Figure 8-10 Function With One Adder Schematic

The following example shows how this change in TEMP’s declaration can yield a significant savings in circuit area, which the figure following the example illustrates.

Writing Circuit Descriptions

Figure 8-11 Using TEMP Declaration to Save Circuit Area

Using State Information

You can also apply design knowledge in sequential designs. Often you can make strong assertions about the value of a signal in a particular state of a finite-state machine. You can describe this information to Foundation Express. The following example shows the VHDL description of a simple state machine that uses two processes.

package STATES is

type STATE_TYPE is (SET0, HOLD0, SET1); end STATES;

use work.STATES.all;

entity MACHINE is port(X, CLOCK: in BIT;

CURRENT_STATE: buffer STATE_TYPE; Z: buffer BIT);

end MACHINE;

VHDL Reference Guide

architecture BEHAVIOR of MACHINE is signal NEXT_STATE: STATE_TYPE; signal PREVIOUS_Z: BIT;begin

-- Process to hold combinatorial logic. COMBIN: process(CURRENT_STATE, X, PREVIOUS_Z)

-- Process to hold synchronous elements (flipflops).

SYNCH: process begin

wait until CLOCK’event and CLOCK = ’1’; CURRENT_STATE <= NEXT_STATE; PREVIOUS_Z <= Z;

end process SYNCH; end BEHAVIOR;

Writing Circuit Descriptions

Figure 8-12 Schematic of Simple State Machine with Two Processes

The following figure shows a schematic of a simple state machine with two processes.In the state hold0, the output Z retains its value from the previous state. To accomplish this, you insert a flip-flop to hold the PREVIOUS_Z. However, you can make some assertions about the value of Z. In state HOLD0, the value of Z is always 0. You can deduce this from the fact that the state HOLD0 is entered only from the state SET0, where Z is always assigned ‘0.’

The following example shows how you can change the VHDL description to use this assertion, resulting in a simpler circuit. The figure following the example illustrates the circuit.

package STATES is

type STATE_TYPE is (SET0, HOLD0, SET1); end STATES;

use work.STATES.all;

entity MACHINE is port(X, CLOCK: in BIT;

CURRENT_STATE: buffer STATE_TYPE; Z: buffer BIT);

end MACHINE;

architecture BEHAVIOR of MACHINE is signal NEXT_STATE: STATE_TYPE;

begin

-- Combinatorial logic.

COMBIN: process(CURRENT_STATE, X)

VHDL Reference Guide

end process COMBIN;

-- Process to hold synchronous elements (flip-flops) SYNCH: process

begin

wait until CLOCK’event and CLOCK = ’1’; CURRENT_STATE <= NEXT_STATE;

end process SYNCH; end BEHAVIOR;

Figure 8-13 Schematic of an Improved State Machine