Chapter 8

Writing Circuit Descriptions

To understand Foundation Express and to write VHDL descriptions that produce efficient synthesized circuits, study the information presented in the following sections of this chapter.

•“How Statements Are Mapped to Logic”

•“Asynchronous Designs”

•“Don’t Care Inference”

•“Synthesis Issues”

Here are some general guidelines for writing efficient circuit descriptions:

•Restructure a design that makes repeated use of several large components, to minimize the number of instantiations.

•In a design that needs some, but not all, of its variables or signals stored during operation, minimize the number of latches or flipflops required.

•Consider collapsing hierarchy for more efficient synthesis.

How Statements Are Mapped to Logic

VHDL descriptions are mapped to combinatorial logic by the creation of blocks of logic. A statement or an operator in a VHDL function can represent a block of combinatorial logic or, in some cases, a latch or register.

The statements shown in the following example represent four logic blocks.

•A comparator that compares the value of B with 10

•An adder that has A and B as inputs