Register and Three-State Inference

more clock cycles behind output C during simulation of the design. However, because Foundation Express ignores the delay information, A and B change values at the same time and so do C and D. This behavior is not the same as in the post-synthesis simulation.

When using delay information in your designs, make sure that the delays do not affect registered values. In general, you can safely include delay information in your description if it does not change the value that gets clocked into a flip-flop.

Understanding Limitations of Register Inference

Foundation Express cannot infer the following components. You must instantiate these components in your VHDL description.

•Flip-flops and latches with three-state outputs

•Flip-flops with bidirectional pins

•Flip-flips with multiple clock inputs

•Multiport latches

•Register banks

Note: Although you can instantiate flip-flops with bidirectional pins, Foundation Express interprets these cells as black boxes.

If you use an if statement to infer D flip-flops, your design must meet the following requirements.

•An edge expression must be the only condition of an if or an elsif clause.

The following if statement is invalid because it has multiple conditions in the if clause.

if (edge and RST = ’1’)

•You can have only one edge expression in an if clause, and the if clause must not have an else clause.

The following if statement is invalid, because you cannot include an else clause when using an edge expression as the if or elsif condition.

if X > 5 then sequential_statement;

elsif edge then