VHDL Reference Guide

Q2

DATA2

CLK

RESET

Q1

DATA1

SLOAD

X8603a

Figure 7-17 Multiple Flip-Flops with Asynchronous and

Synchronous Controls

A flip-flop inference has specific limitations. See the “Understanding Limitations of Register Inference” section of this chapter.

Inferring JK Flip-Flops

When you infer a JK flip-flop, make sure you can control the J, K, and clock signals from the top-level design ports to ensure that simulation can initialize the design.The following sections provide code examples, inference reports, and figures for these types of JK flip-flops.

•JK flip-flop

•JK flip-flop with asynchronous set and reset

Register and Three-State Inference

JK Flip-Flop When you infer a JK flip-flop, make sure you can control the J, K, and clock signals from the top-level design ports to ensure that simulation can initialize the design.

In the JK flip-flop, the J and K signals act as active-high synchronous set and reset. Use the sync_set_reset directive to indicate that the J and K signals are the synchronous set and reset for the design.

Table 7-1 Truth Table for JK Flip-Flop

The following example provides the VHDL code that implements the JK flip-flop described in the truth table.

library IEEE, synopsys;

use IEEE.std_logic_1164.all; use synopsys.attributes.all;

entity jk is

port(J, K, CLK : in std_logic; Q_out : out std_logic );

attribute sync_set_reset of J, K : signal is ”true”;

end jk;

architecture rtl of jk is signal Q : std_logic;

begin

infer: process

variable JK : std_logic_vector ( 1 downto 0); begin

wait until (CLK’event and CLK = ’1’); JK <= (J & K);

case JK is

when ”01” => Q <= ’0’; when ”10” => Q <= ’1’; when ”11” => Q <= not (Q); when ”00” => Q <= Q;

when others => Q <= ’X’;

VHDL Reference Guide

end case;

end process infer;

Q_out <= Q; end rtl;

The following example shows the inference report generated by Foundation Express for a JK flip-flop, and the figure following the report, “JK Flip-Flop,” shows the inferred flip-flop.

Q_reg

Sync-reset: J’ K

Sync-set: J K’

Sync-toggle: J K

Sync-set and Sync-reset ==> Q: X

Figure 7-18 JK Flip-Flop

JK Flip-Flop With Asynchronous Set and Reset Use the sync_set_reset attribute to indicate the JK function. Use the one_hot attribute to prevent priority encoding of the J and K signals.

The following example provides the VHDL template for a JK flip-flop with asynchronous set and reset.

library IEEE, synopsys;

use IEEE.std_logic_1164.all; use synopsys.attributes.all;

entity jk_async_sr is

port (SET, RESET, J, K, CLK : in std_logic; Q_out : out std_logic );

Register and Three-State Inference

attribute sync_set_reset of J, K : signal is ”true”;

attribute one_hot of SET,RESET : signal is ”true”; end jk_async_sr;

architecture rtl of jk_async_sr is signal Q : std_logic;

begin

infer : process (CLK, SET, RESET)

variable JK : std_logic_vector (1 downto 0); begin

if (RESET = ’1’) then Q <= ’0’;

elsif (SET = ’1’) then Q <= ’1’;

elsif (CLK’event and CLK = ’1’) then JK <= (J & K);

case JK is

when ”01” => Q <= ’0’; when ”10” => Q <= ’1’; when ”11” => Q <= not(Q); when ”00” => Q <= Q; when others => Q <= ’X’;

end case; end if;

end process infer; Q_out <= Q;

end rtl;

The following table shows the inference report Foundation Express generates for a JK flip-flop with asynchronous set and reset, and the figure following the report, “JK Flip-Flop with Asynchronous Set and Reset,” shows the inferred flip-flop.

Q_reg

Async-reset: RESET

Async-set: SET

Sync-reset: J’ K

Sync-set: J K’

Sync-toggle: J K