VHDL Reference Guide

under some, but not all, conditions. The following example shows an invalid use of the conditionally assigned variable VALUE.

signal X, Y : std_logic;

. . .

process

variable VALUE : std_logic; begin

if (condition) then VALUE <= X;

end if;

Y <= VALUE; -- Invalid read of variable VALUE end process;

Inferring Master-Slave Latches

You can infer two-phase systems by using D latches.The following example shows a simple two-phase system with clocks MCK and

SCK. The inference reports follow the example. The figure “TwoPhase Clocks” shows the inferred latch.

library IEEE;

use IEEE.std_Logic_1164.all;

entity LATCH_VHDL is

port(MCK, SCK, DATA: in std_logic; Q : out std_logic );

end LATCH_VHDL;

architecture rtl of LATCH_VHDL is signal TEMP : std_logic;

begin

process (MCK, DATA) begin if (MCK = ’1’) then

TEMP <= DATA; end if;

end process;

process (SCK, TEMP) begin if (SCK = ’1’) then

Q <= TEMP; end if;

end process;