Register and Three-State Inference

attribute one_hot signal_name_list : signal is ”true”;

Inferring Latches

In simulation, a signal or variable holds its value until that output is reassigned. In hardware, a latch implements this holding-of-state capability. Foundation Express supports inference of the following types of latches.

•SR latch

•D latch

•Master-slave latch

The following sections provide details about each of these latch types.

Inferring Set/Reset (SR) Latches

Use SR latches with caution, because they are difficult to test. If you decide to use SR latches, you must verify that the inputs are hazardfree (do not glitch). During synthesis, Foundation Express does not ensure that the logic driving the inputs is hazard-free.

The following example of an SR latch provides the VHDL code that implements the SR latch described in the truth table. The inference report following the truth table for an SR latch shows the inference report that Foundation Express generates.

The following example shows an SR latch.

library IEEE, synopsys;

use IEEE.std_logic_1164.all; use synopsys.attributes.all;

entity sr_latch is

port (SET, RESET : in std_logic; Q : out std_logic );

attribute async_set_reset of SET, RESET :

VHDL Reference Guide

signal is ”true”; end sr_latch;

architecture rtl of sr_latch is begin

infer: process (SET, RESET) begin if (SET = ’0’) then

Q <= ’1’;

elsif (RESET = ’0’) then Q <= ’0’;

end if;

end process infer;

end rtl;

The example below shows an inference report for an SR latch and its schematic.

y_reg

Async-reset: RESET’ Async-set: SET’

Async-set and Async-reset ==> Q: 1

Q

RESET

SET

X8590a

Figure 7-1 SR Latch

Register and Three-State Inference

Inferring D Latches

When you do not specify the resulting value for an output under all conditions, as in an incompletely specified if statement, Foundation Express infers a D latch.

For example, the if statement in the following example infers a D latch because there is no else clause. The resulting value for output Q is specified only when input enable has a logic 1 value. As a result, output Q becomes a latched value.

process(DATA, GATE) begin if (GATE = ’1’) then

Q <= DATA; end if;

end process;

To avoid latch inference, assign a value to the signal under all conditions, as shown in the following example.

process(DATA, GATE) begin if (GATE = ’1’) then

Q <= DATA; else

Q <= ’0’; end if;

end process;

Variables declared locally within a subprogram do not hold their value over time, because each time a subprogram is called, its variables are reinitialized. Therefore, Foundation Express does not infer latches for variables declared in subprograms. In the following example, Foundation Express does not infer a latch for output Q.

function MY_FUNC(DATA, GATE : std_logic) return std_logic is

variable STATE: std_logic; begin

if (GATE = ’1’) then STATE <= DATA;

end if; return STATE;

end;

. . .

Q <= MY_FUNC(DATA, GATE);

VHDL Reference Guide

The following sections provide code examples, inference reports, and figures for these types of D latches.

•Simple D latch

•D latch with asynchronous set

•D latch with asynchronous reset

•D latch with asynchronous set and reset

Simple D Latch When you infer a D latch, control the gate and data signals from the top-level design ports or through combinatorial logic. Gate and data signals that can be controlled ensure that simulation can initialize the design.

The following example provides the VHDL template for a D latch. Foundation Express generates the inference report shown after the example for a D latch. The figure “D Latch” shows the inferred latch.

library IEEE;

use IEEE.std_logic_1164.all;

entity d_latch is

port (GATE, DATA: in std_logic; Q : out std_logic );

end d_latch;

architecture rtl of d_latch is begin

infer: process (GATE, DATA) begin if (GATE = ’1’) then

Q <= DATA; end if;

end process infer;

end rtl;

The example below shows an inference report for a D latch.

Register Name Type Width Bus MB AR AS SR SS ST

Q_reg

reset/set:none

Register and Three-State Inference

the async_set_reset attribute to direct Foundation Express to the asynchronous set (AS) pins of the inferred latch.

The following example provides the VHDL template for a D latch with an asynchronous set. Foundation Express generates the inference report shown following the example for a D latch with asynchronous set. The figure “D Latch with Asynchronous Set” shows the inferred latch.

library IEEE, synopsys;

use IEEE.std_logic_1164.all; use synopsys.attributes.all;

entity d_latch_async_set is

port (GATE, DATA, SET : in std_logic; Q : out std_logic );

attribute async_set_reset of SET : signal is ”true”;

end d_latch_async_set;

architecture rtl of d_latch_async_set is begin

infer: process (GATE, DATA, SET) begin if (SET = ’0’) then

Q <= ’1’;

elsif (GATE = ’1’) then Q <= DATA;

VHDL Reference Guide

end if;

end process infer;

end rtl;

The following example shows an inference report for a D latch with asynchronous set.

Register Name Type Width Bus MB AR AS SR SS ST

Q_reg

Async-set: SET’

DATA

Q

GATE

SET

X8592

Figure 7-3 D Latch with Asynchronous Set

Note: Because the target technology library does not contain a latch with an asynchronous set, Foundation Express synthesizes the set logic by using combinatorial logic.

D Latch with Asynchronous Reset The template in this section uses the async_set_reset attribute to direct Foundation Express to the asynchronous reset (AR) pins of the inferred latch.

The following example provides the VHDL template for a D latch with an asynchronous reset. Foundation Express generates the inference report shown following the example for a D latch with asynchronous reset. The figure “D Latch with Asynchronous Reset” shows the inferred latch.

Register and Three-State Inference

library IEEE, synopsys;

use IEEE.std_logic_1164.all; use synopsys.attributes.all;

entity d_latch_async_reset is

port (GATE, DATA, RESET : in std_logic; Q : out std_logic );

attribute async_set_reset of RESET : signal is ”true”;

end d_latch_async_reset;

architecture rtl of d_latch_async_reset is begin

infer : process (GATE, DATA, RESET) begin if (RESET = ’0’) then

Q <= ’0’;

elsif (GATE = ’1’) then Q <= DATA;

end if;

end process infer;

end rtl;

The following example shows an inference report for a D latch with asynchronous reset.

Q_reg

Async-reset: RESET’

VHDL Reference Guide

GATE

RESET

X8593a

Figure 7-4 D Latch with Asynchronous Reset

D Latch with Asynchronous Set and Reset The following example provides the VHDL template for a D latch with an activelow asynchronous set and reset. This template uses the async_set_reset_local attribute to direct Foundation Express to the asynchronous signals in the infer process.

The template in the following example uses the one_cold attribute to prevent priority encoding of the set and reset signals. If you do not specify the one_cold attribute, the set signal has priority, because it is used as the condition for the if clause. Foundation Express generates the inference report shown following the example for a D latch with asynchronous set and reset. The figure “D Latch with Asynchronous Set and Reset” shows the inferred latch.

library IEEE, synopsys;

use IEEE.std_logic_1164.all; use synopsys.attributes.all;

entity d_latch_async is

port (GATE, DATA, SET, RESET :in std_logic; Q : out std_logic );

attribute one_cold of SET, RESET : signal is ”true”;

end d_latch_async;

architecture rtl of d_latch_async is attribute async_set_reset_local of infer :

Register and Three-State Inference