Concurrent Statements

For more information about arrays, see “Array Types” section of the “Data Types” chapter.

if...generate Statements

The syntax follows.

label: if expression generate { concurrent_statement }

end generate [ label ] ;

•label identifies (names) this statement.

•expression is any expression that evaluates to a Boolean value.

•concurrent_statement is any of the statements described in this chapter, including other generate statements.

Note: Unlike the if statement described in the “if Statements” section of the “Sequential Statements” chapter, the if...generate statement has no else or elsif branches.

You can use the if...generate statement to generate a regular structure that has different circuitry at its ends. Use a for...generate statement to iterate over the desired width of a design and use a set of if...generate statements to define the beginning, middle, and ending sets of connections.

The following example shows a technology-independent description of an N-bit serial-to-parallel converter. Data is clocked into an N-bit buffer from right to left. On each clock cycle, each bit in an N-bit buffer is shifted up 1 bit, and the incoming DATA bit is moved into the low-order bit. The resulting design follows the example.

entity CONVERTER is generic(N: INTEGER := 8);

port(CLK, DATA: in BIT;

CONVERT: buffer BIT_VECTOR(N-1 downto 0)); end CONVERTER;

architecture BEHAVIOR of CONVERTER is signal S : BIT_VECTOR(CONVERT’range);

begin

G: for I in CONVERT’range generate

G1: -- Shift (N-1) data bit into high-order bit if (I = CONVERT’left) generate

VHDL Reference Guide

process begin

wait until (CLK’event and CLK = ‘1’); CONVERT(I) <= S(I-1);

end process; end generate G1;

G2: -- Shift middle bits up if (I > CONVERT’right and

I < CONVERT’left) generate

S(I) <= S(I-1) and CONVERT(I);

process begin

wait until (CLK’event and CLK =’1’); CONVERT(I) <= S(I-1);

end process; end generate G2;

G3: -- Move DATA into low-order bit if (I = CONVERT’right) generate

process begin

wait until (CLK’event and CLK = ‘1’); CONVERT(I) <= DATA;

end process;

S(I) <= CONVERT(I); end generate G3;

end generate G; end BEHAVIOR;

Concurrent Statements

Figure 6-11 Design of N-Bit Serial-to-Parallel Converter

VHDL Reference Guide