Concurrent Statements

END COMPONENT; BEGIN

u1 : leaf PORT MAP (

clk => clk, data => d_in(0),

Qout => q_out(0));

The following example shows how you can express the information in the previous example in a direct component instantiation statement.

ARCHITECTURE struct OF root IS BEGIN

u1 : entity work.leaf(rtl) port map (

clk => clk, data => d_in(0),

Qout => q_out(0));

generate Statements

A generate statement creates zero or more copies of an enclosed set of concurrent statements. The two kinds of generate statements follow.

•For...generate—the number of copies is determined by a discrete range.

•If...generate—zero or one copy is made, conditionally.

for...generate Statements

The syntax follows.

label: for identifier in range generate { concurrent_statement }

end generate [ label ] ;

•label, which is required, names this statement and is useful for building nested generate statements.

•identifier is specific to the for...generate statement.

•Identifier is not declared elsewhere. It is automatically declared by the generate statement itself and is local to the statement. A for...generate identifier overrides any other

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identifier with the same name, but only within the for...generate statement.

•The value of identifier can be read only inside its for...generate statement (identifier does not exist outside the statement). You cannot assign a value to a for...generate identifier.

•The value of identifier cannot be assigned to any parameter whose mode is out or inout.

•range must be a computable integer range, in either of two forms.

integer_expression to integer_expression integer_expression downto integer_expression

•integer_expression evaluates to an integer. Each concurrent_statement can be any of the statements described in this chapter, including other generate statements.

Steps in the Execution of a for...generate Statement

A for...generate statement executes as follows.

1.A new local integer variable is declared with the name identifier.

2.The identifier receives the first value of range, and each concurrent statement executes once.

3.The identifier receives the next value of range, and each concurrent statement executes once more.

4.Step 3 repeats until the identifier receives the last value in the range and each concurrent statement executes for the last time, Execution continues with the statement following end generate. The loop identifier is deleted.

The following example shows a code fragment that combines and interleaves two 4-bit arrays, A and B, into an 8-bit array, C. The resulting design is shown in the figure following the example.

signal A, B : bit_vector(3 downto 0);

GEN_LABEL: for I in 3 downto 0 generate

C(2*I + 1) <= A(I) nor X;

Concurrent Statements

NR2 C[3]

A[1]

B[2]

NR2 C[4]

X

VHDL Reference Guide

Common Usage of a for...generate Statement

The most common use of the generate statement is to create multiple copies of components, processes, or blocks. The following example and figure demonstrates this use with components. (The example and figure following this example and figure show this usage with processes.)

The following example shows VHDL array attribute ’range used with the for...generate statement to instantiate a set of COMP components that connect corresponding elements of bit vectors A and B. The resulting design follows each of the examples.

component COMP

port (X : in bit; Y : out bit);

end component;

. . .

signal A, B: BIT_VECTOR(0 to 7);

. . .

GEN: for I in A’range generate U: COMP port map (X => A(I),

Y => B(I));

end generate GEN;

COMP

A [0] B [0]

COMP

A [1] B [1]

COMP

A [2] B [2]

COMP

A [3] B [3]

COMP

A [4] B [4]

COMP

A [5] B [5]

COMP

A [6] B [6]

COMP

A [7] B [7]

X8648

Figure 6-10 Design of COMP components Connecting Bit Vectors A and B