Concurrent Statements

Concurrent Signal Assignments

A concurrent signal assignment is equivalent to a process containing a sequential assignment. Thus, each concurrent signal assignment defines a new driver for the assigned signal. This section discusses the three forms of concurrent signal assignment.

Simple Concurrent Signal Assignments

The syntax of the simplest form of the concurrent signal assignment follows.

target <= expression;

target is a signal that receives the value of an expression.

The following example shows the value of expressions A and B concurrently assigned to signal Z.

BLK: block

signal A, B, Z: BIT; begin

Z <= A and B; end block BLK;

The other two forms of concurrent signal assignment are conditional signal assignment and selected signal assignment.

Conditional Signal Assignments

The syntax of the conditional signal assignment follows.

target <= { expression when condition else } expression;

target is a signal that receives the value of an expression. The expression used is the first one whose Boolean condition is TRUE.

When Foundation Express executes a conditional signal assignment statement, it tests each condition in the order written.

•Foundation Express assigns to the target the expression of the first condition that evaluates to TRUE.

•If no condition evaluates to TRUE, Foundation Express assigns the final expression to the target.

•If two or more conditions are TRUE, Foundation Express assigns only the first one to the target.

VHDL Reference Guide

The following example shows a conditional signal assignment. The target is the signal Z, which is assigned from one of the signals A, B, or C. The signal depends on the value of the expressions ASSIGN_A and ASSIGN_B. The resulting design is shown in the figure following the example.

Note: The A assignment takes precedence over B, and B takes precedence over C, because the first TRUE condition controls the assignment.

Z <= A when ASSIGN_A = ’1’ else

B when ASSIGN_B = ’1’ else

C;

MUX21H

C

B

MUX21H

ASSIGN_B

Z

A

ASSIGN_A

X8662

Figure 6-6 Conditional Signal Assignment Design

The following example shows a process equivalent to the example of the conditional signal assignment.

process(A, ASSIGN_A, B, ASSIGN_B, C) begin

if ASSIGN_A = ’1’ then Z <= A;

elsif ASSIGN_B = ’1’ then Z <= B;

else

Z <= C; end if;

end process;

Concurrent Statements

Selected Signal Assignments

The syntax of the selected signal assignment follows.

with choice_expression select

target <= { expression when choices, } expression when choices;

target is a signal that receives the value of an expression. The expression selected is the first one whose choices include the value of choice_expression.

Each choice can be either of the following.

•A static expression (such as 3)

•A static range (such as 1 to 3).

The value of each choice the target signal receives has to match the value or values of choice_expression.

If the value of choice_expression is a static range, each value in the range must be covered by one choice in the expression.

The final choice can be others, which matches all remaining (unchosen) values in the range of the choice_expression type. The others choice, if present, matches choice_expression only if none of the other choices match. You can use others as the final choice only if the value of choice_expression is a range.

The with...select statement evaluates choice_expression and compares that value to each choice value. The when clause with the matching choice value has its expression assigned to target.

The following restrictions are placed on choices.

•No two choices can overlap.

•If no others choice is present, all possible values of choice_expression must be covered by the set of choices.

The following example shows target Z assigned from A, B, C, or D. The assignment depends on the current value of CONTROL. The resulting design is shown in the figure following the example.

signal A, B, C, D, Z: BIT;

signal CONTROL: bit_vector(1 down to 0);

. . .

with CONTROL select Z <= A when "00",