Chapter 6

Concurrent Statements

A VHDL architecture construct comprises a set of interconnected concurrent statements, such as blocks or processes, that describe an overall design in terms of behavior or structure. Concurrent statements in a design execute simultaneously, unlike sequential statement, which execute one after another.

This chapter describes concurrent statements and their function. The chapter is divided into the following sections.

•“Overview”

•“process Statements”

•“block Statements”

•“Concurrent Versions of Sequential Statements”

•“Component Instantiation Statements”

•“Direct Instantiation”

•“generate Statements”

Overview

The two main concurrent statements are the following.

•Process statements

•Block statements

VHDL provides two concurrent versions of sequential statements.

•Concurrent procedure calls

•Concurrent signal assignments