Sequential Statements
architecture ARCH of TEST is begin
process begin
Z <= MUX_FUNC(not A, A, C); end process;
end ARCH;
Figure 5-12 Circuit Design without Component Implication
Directives
wait Statements
A wait statement suspends a process until Foundation Express detects a positive-going edge or negative-going edge on a signal. The syntax follows.
wait until signal = value ;
wait until signal’event and signal = value ; wait until not signal’stable
and signal = value ;
signal is the name of a single-bit signal—a signal of an enumerated type encoded with one bit (see the “Data Types” chapter). The value must be one of the literals of the enumerated type. If the signal type is BIT, the awaited value is either ’1,’ for a positive-going edge, or ’0,’ for a negative-going edge.
Note: Three forms of the wait statement (a subset of IEEE VHDL), shown in the previous syntax and in the following example, are specific to the current implementation of Foundation Express.
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Inferring Synchronous Logic
A wait statement implies synchronous logic, where signal is usually a clock signal. The “Combinatorial Versus Sequential Processes” section of this chapter describes how Foundation Express infers and implements this logic.
The following example shows three equivalent wait statements (all positive-edge triggered).
wait until CLK = ’1’;
wait until CLK’ event and CL = ‘1’; wait until not CLK’stable and CLK = ’1’;
When a circuit is synthesized, the hardware in the three forms of wait statements does not differ.
The following example shows a wait statement that suspends a process until the next positive edge (a 0-to-1 transition) on signal CLK.
signal CLK: BIT;
...
process begin
wait until CLK’event and CLK = ‘1’;
-- Wait for positive transition (edge)
...
end process;
Note: IEEE VHDL specifies that a process containing a wait statement must not have a sensitivity list. For more information, see the
“process Statements” section of the “Concurrent Statements” chapter.
The following example shows how a wait statement is used to describe a circuit where a value is incremented on each positive clock edge.
process begin
y <= 0;
wait until (clk’event and clk = ‘1’); while (y < MAX) loop
wait until (clk’event and clk = ‘1’); x <= y ;
y <= y + 1; end loop;
end process;
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Sequential Statements
The following example shows how multiple wait statements describe a multicycle circuit. The circuit provides an average value of its input A over four clock cycles.
process |
|
begin |
|
wait until |
CLK’event and CLK = ‘1’; |
AVE <= A; |
|
wait until |
CLK’event and CLK = ‘1’; |
AVE <= AVE |
+ A; |
wait until |
CLK’event and CLK = ‘1’; |
AVE <= AVE |
+ A; |
wait until |
CLK’event and CLK = ‘1’; |
AVE <= (AVE + A)/4; end process;
The following example shows two equivalent descriptions. The first description uses implicit state logic, and the second uses explicit state logic.
--Implicit State Logic process
begin
wait until CLK’event and CLK = ‘1’; if (CONDITION) then
X <= A; else
wait until CLK’event and CLK = ‘1’; end if;
end process;
-- Explicit State Logic type STATE_TYPE is (SO, S1); variable STATE : STATE_TYPE;
...
process begin
wait until CLK’event and CLK = ‘1’; case STATE is
when S0 =>
if (CONDITION) then X <= A;
STATE := S0; else
STATE := S1; end if;
when S1 =>
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STATE := S0; end case;
end process;
Note: You can use wait statements anywhere in a process except in for...loop statements or subprograms. However, if any path through the logic contains one or more wait statements, all paths must contain at least one wait statement.
The following example shows how to describe a circuit with synchronous reset using wait statements in an infinite loop. Foundation Express checks the reset signal immediately after each wait statement. The assignment statements in the following example (X <= A; and Y <= B;) represent the sequential statements used to implement the circuit.
process begin
RESET_LOOP: loop
wait until CLOCK’event and CLOCK = ‘1’; next RESET_LOOP when (RESET = ’1’);
X <= A;
wait until CLOCK’event and CLOCK = ‘1’; next RESET_LOOP when (RESET = ’1’);
Y <= B;
end loop RESET_LOOP; end process;
The example below shows two invalid uses of wait statements that are specific to Foundation Express.
...
type COLOR is (RED, GREEN, BLUE); attribute ENUM_ENCODING : STRING;
attribute ENUM_ENCODING of COLOR : type is -100 010 001";
signal CLK : COLOR;
...
process begin
wait until CLK’event and CLK = RED;
-- Illegal: clock type is not encoded with 1 bit
...
end;
...
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