VHDL Reference Guide

(such as 3 to 5 => or 7 downto 0 =>) to indicate a sequence of element indexes.

An aggregate can use both positional and named notation. It is not necessary to specify all element indexes in an aggregate. All unassigned values are given a value by including others => expression as the last element of the list.

The following example shows several aggregates representing the same value.

subtype MY_VECTOR is BIT_VECTOR(1 to 4);

The others expression must be the only expression in the aggregate. The following example shows two equivalent aggregates.

MY_VECTOR’(others => ’1’);

MY_VECTOR’(’1’, ’1’, ’1’, ’1’);

To use an aggregate as the target of an assignment statement, see the

“Assignment Statements and Targets” section of the “Sequential Statements” chapter.

Attributes

VHDL defines attributes for various types. A VHDL attribute takes a variable or signal of a given type and returns a value. The syntax of an attribute follows.

object’attribute

Foundation Express supports the following predefined VHDL attributes for use with arrays, as described in the “Array Types” section of the “Data Types” chapter.

•left

•right

•high

•low

•length

Expressions

•range

•reverse_range

Foundation Express also supports the following predefined VHDL attributes to use with wait and if statements, as described in the “Register and Three-State Inference” chapter.

•event

•stable

In addition to supporting the predefined VHDL attributes listed above, Foundation Express has a defined set of synthesis-related attributes. You can include these Foundation Express-specific attributes in your VHDL design description to direct Foundation Express during optimization.

Expressions

Operands can themselves be expressions. You create expression operands by surrounding an expression with parentheses, such as (A nand B).

Function Calls

A function call executes a named function with the given parameter values. The value returned to an operator is the function’s return value. The syntax of a function call follows.

function_name ( [parameter_name =>] expression

{, [parameter_name =>] expression }

•function_name is the name of a defined function.

•The optional parameter_name is the name of formal parameters, as defined by the function. Each expression provides a value for its parameter and must evaluate to a type appropriate for that parameter.

You can specify parameters in positional or named notation, like aggregate values.

In positional notation, the parameter_name => construct is omitted. The first expression provides a value for the function’s first parameter, the second expression provides a value for the second parameter, and so on.

VHDL Reference Guide

In named notation, parameter_name => is specified before an expression; the named parameter gets the value of that expression.

You can mix positional and named expressions in the same function call if you put all positional expressions before named parameter expressions.

The following example shows a function declaration and several equivalent function calls.

function FUNC(A, B, C: INTEGER) return BIT;

. . .

FUNC(1, 2, 3)

FUNC(B => 2, A => 1, C => 7 mod 4) FUNC(1, 2, C => -3+6)

Identifiers

Identifiers are probably the most common operand. An identifier is the name of a constant, variable, signal, entity, port, subprogram, or parameter and returns the object’s value to an operand.

Identifiers that contain special characters, begin with numbers, or have the same name as a keyword can be specified as an extended identifier. An extended identifier starts with a backslash character (\), followed by a sequence of characters, followed by another backslash character (\).

The following example shows some extended identifiers.

\a+b\ \3state\ \type\ \(a&b)|c\

The following example shows several kinds of identifiers and their usages. All identifiers appear in bold type.

entity EXAMPLE is

port (INT_PORT: in INTEGER; BIT_PORT: out BIT);

end;

. . .

signal BIT_SIG: BIT; signal INT_SIG: INTEGER;

. . .

INT_SIG <= INT_PORT; -- Signal assignment from port BIT_PORT <= BIT_SIG; -- Signal assignment to port

Expressions

function FUNC(INT_PARAM: INTEGER) return INTEGER;

end function;

. . .

constant CONST: INTEGER := 2; variable VAR: INTEGER;

. . .

VAR := FUNC(INT_PARAM => CONST); -- Function call

Indexed Names

An indexed name identifies one element of an array variable or signal. The syntax of an indexed name follows.

identifier ( expression )

identifier is the name a signal or variable of an array type. The expression must return a value within the array’s index range. The value returned to an operator is the specified array element.

If the expression is computable (see the “Computable Operands” section of this chapter), the operand is synthesized directly. If the expression is not computable, a circuit is synthesized that extracts the specified element from the array.

The following example shows two indexed names—one computable and one not computable. The figure for the resulting synthesized circuit design follows the example.

signal A, B: BIT_VECTOR(0 to 3); signal I: INTEGER range 0 to 3; signal Y, Z: BIT;