VHDL Reference Guide

To understand expressions for VHDL, consider the individual components of operators and operands.

Operators

•Logical Operators

•Relational Operators

•Adding Operators

•Unary (Signed) Operators

•Multiplying Operators

•Miscellaneous Arithmetic Operators Operands

•Computable Operands

•Literals

•Identifiers

•Indexed Names

•Slice Names

•Function Calls

•Qualified Expressions

•Type Conversions

Operators

A VHDL operator is characterized by the following.

•Name

•Computation (function)

•Number of operands

•Type of operands (such as Boolean or Character)

•Type of result value

Expressions

You can define new operators, like functions, for any type of operand and result value. The predefined VHDL operators are listed in the table below.

Table 4-1 Predefined VHDL Operators

Each row in the table lists operators with the same precedence. Each row’s operators have greater precedence than those in the row above. An operator’s precedence determines whether it is applied before or after adjoining operators.

The following example shows several expressions and their interpretations.

VHDL allows existing operators to be overloaded, that is, applied to new types of operands. For example, the AND operator can be overloaded to work with a new logic type. For more information, see the “Operator Overloading” section in the “Design Descriptions” chapter.

Logical Operators

Operands of a logical operator must be of the same type. The logical operators AND, OR, NAND, NOR, XOR, and NOT accept operands of type BIT or type BOOLEAN, and one-dimensional arrays of BIT or BOOLEAN. Array operands must be the same size. A logical operator applied to two array operands is applied to pairs of the two arrays’ elements.

The following example shows logical signal declarations and their logical operations.

VHDL Reference Guide

signal A, B, C: BIT_VECTOR(3 downto 0); signal D, E, F, G: BIT_VECTOR(1 downto 0); signal H, I, J, K: BIT;

signal L, M, N, O, P: BOOLEAN;

Figure 4-1 Design Schematic for Logical Operators

Normally, to use more than two operands in an expression, you must use parentheses to group the operands. An exception is that you can combine a sequence of AND, OR, XNOR, or XOR operators without parentheses, such as the following sequence that uses the same oper- ator—AND.

A and B and C and D

However, a sequence that contains more than one of these operators requires parentheses to indicate which two operands are to be paired. In the following sequence, AND is the first operator, OR is the second.

A and B or C

Expressions

Parentheses should be used in one of two ways, as shown in the following example.

(A and B) or C

or

A and (B or C)

Relational Operators

Relational operators, such as = or >, compare two operands of the same base type and return a BOOLEAN value.

IEEE VHDL defines the equality (=) and inequality (/=) operators for all types. Two operands are equal if they represent the same value. For array and record types, IEEE VHDL compares corresponding elements of the operands.

IEEE VHDL defines the ordering operators (<, <=, >, and >=) for all enumerated types, integer types, and one-dimensional arrays of enumeration or integer types.

The internal order of a type’s values determines the result of the ordering operators. Integer values are ordered from negative infinity to positive infinity. Enumerated values are in the same order as they were declared, unless you have changed the encoding.

Note: If you set the encoding of your enumerated types (“Enumeration Encoding” section of the “Data Types” chapter), the ordering operators compare your encoded value ordering, not the declaration ordering. Because this interpretation is specific to Foundation Express, a VHDL simulator continues to use the declaration’s order of enumerated types.

Arrays are ordered alphabetically. Foundation Express determines the relative order of two array values by comparing each pair of elements in turn, beginning from the left bound of each array’s index range. If a pair of array elements is not equal, the order of the different elements determines the order of the arrays. For example, bit vector “101011” is less than “1011” because the fourth bit of each vector is different, and ‘0’ is less than ‘1.’

If the two arrays have different lengths, and the shorter array matches the first part of the longer array, the shorter one is ordered before the longer. Thus, the bit vector “10” is less than “101000.”

VHDL Reference Guide

Arrays are compared from left to right, regardless of their index ranges (to or downto).

The following example shows several expressions that evaluate to

TRUE.

’1’ = ’1’ "101" = "101"

"1" > "011" -- Array comparison "101" < "110"

To interpret bit vectors such as “011” as signed or unsigned binary numbers, use the relational operators defined in the std_logic_arith package (listed in the “Foundation Express Packages” chapter). The third line in the above example evaluates FALSE if the operands are of type UNSIGNED.

UNSIGNED’"1" < UNSIGNED’"011" -- Numeric comparison

The following example shows some relational expressions. The resulting synthesized circuit follows the example.

signal A, B: BIT_VECTOR(3 downto 0); signal C, D: BIT_VECTOR(1 downto 0); signal E, F, G, H, I, J: BOOLEAN;

G <= (A = B);

H <= (C < D);

I <= (C >= D);

J <= (E > F);